NVM-CIM accelerators; AI HW energy; TSV faults; Si/SiGe multi-layer stacks; BPR to suppress substrate leakage in CFETs; small-pitch interconnects; DRAM read disturbance; HW-aligned sparse attention architecture.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators | TSMC |
| Life-Cycle Emissions of AI Hardware: A Cradle-To-Grave Approach and Generational Trends | |
| Low Cost TSV Repair Architecture Using Switch-Based Matrix for Highly Clustered Faults | Yonsei University |
| Epitaxial Si/SiGe Multi-Stacks: From Stacked Nano-Sheet to Fork-Sheet and CFET Devices | imec and Ghent University, et al. |
| Buried power rail to suppress substrate leakage in complementary field effect transistor (CFET) | Korea University and Sungkyunkwan University |
| Facilitating Small-Pitch Interconnects with Low-Temperature Solid-Liquid Interdiffusion Bonding | Aalto University in Finland |
| Variable Read Disturbance: An Experimental Analysis of Temporal Variation in DRAM Read Disturbance | ETH Zurich and Rutgers University |
| Native Sparse Attention: Hardware-Aligned and Natively Trainable Sparse Attention | DeepSeek, Peking University and University of Washington |
Find all technical papers here.
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