Chip Industry Week In Review

By The SE Staff - 26 Jul, 2024 - Comments: 0

The U.S. Department of Commerce and Amkor Technology signed a deal to provide up to $400 million in funding, under the CHIPS and Science Act, to build a previously announced end-to-end advanced packaging plant. The combined funding is expected to total about $2 billion. The new facility will add some 2,000 jobs in Peoria, Arizona. The SK hynix Board approved its Yongin Semiconductor Cluster... » read more

Improving Performance and Power Efficiency By Safely Eliminating Load Instruction Execution (ETH Zürich, Intel)

By Technical Paper Link - 22 Jul, 2024 - Comments: 0

A technical paper titled “Constable: Improving Performance and Power Efficiency by Safely Eliminating Load Instruction Execution” was published by researchers at ETH Zürich and Intel Corporation. This paper earned the Best Paper Award in the International Symposium on Computer Architecture (ISCA). Abstract: "Load instructions often limit instruction-level parallelism (ILP) in modern pr... » read more

Chip Industry Technical Paper Roundup: July 16

By Linda Christensen - 16 Jul, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library. [table id=244 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review

By The SE Staff - 12 Jul, 2024 - Comments: 0

The U.S. Department of Commerce issued a notice of intent  to fund new R&D activities to establish and accelerate domestic advanced packaging capacity. CHIPS for America expects to award up to $1.6 billion in funding innovation across five R&D areas, as outlined in the vision for the National Advanced Packaging Manufacturing Program (NAPMP), with about $150 million per award in each... » read more

Analysis Of The On-DRAM-Die Read Disturbance Mitigation Method: Per Row Activation Counting

By Technical Paper Link - 10 Jul, 2024 - Comments: 0

A technical paper titled “Understanding the Security Benefits and Overheads of Emerging Industry Solutions to DRAM Read Disturbance” was published by researchers at ETH Zürich and TOBB University of Economics and Technology. Abstract: "We present the first rigorous security, performance, energy, and cost analyses of the state-of-the-art on-DRAM-die read disturbance mitigation method, Per... » read more

Roadmap To Neuromorphic Computing (Collaboration of 27 Universities/Companies)

By Technical Paper Link - 09 Jul, 2024 - Comments: 0

A technical paper titled “Roadmap to Neuromorphic Computing with Emerging Technologies” was published by researchers at University College London, Politecnico di Milano, Purdue University, ETH Zurich and numerous other institutions. Summary: "The roadmap is organized into several thematic sections, outlining current computing challenges, discussing the neuromorphic computing approach, ana... » read more

Chip Industry Week In Review

By The SE Staff - 03 Jul, 2024 - Comments: 0

Early version due to U.S. holiday. The U.S. government announced a new $504 million funding round for 12 Regional Technology and Innovation Hubs (Tech Hubs) for semiconductors, clean energy, biotechnology, AI, quantum computing, and more. Among the recipients: NY SMART I-Corridor Tech Hub (New York): $40 million for semiconductor manufacturing; Headwaters Hub (Montana): $41 million f... » read more

Chip Industry Technical Paper Roundup: June 18

By Linda Christensen - 18 Jun, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=234 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review

By The SE Staff - 14 Jun, 2024 - Comments: 0

Samsung unveiled its latest 2nm and 4nm process nodes, plus its AI solutions during the Samsung Foundry Forum. The company also introduced an aggressive roadmap for the next few years that includes 3D-ICs with logic-on-logic, starting in 2025; custom HBM with built-in logic; backside power delivery on 2nm technology in 2027; and co-packaged optics. In presentations at the event, the company als... » read more

Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich)

By Technical Paper Link - 13 Jun, 2024 - Comments: 0

A new technical paper titled "RISC-H: Rowhammer Attacks on RISC-V" was published by researchers at ETH Zurich. RISC-H will be presented at DRAMSec (co-located with ISCA 2024) Abstract: "The first high-end RISC-V CPU with DDR4 support has been released just a few months ago. There are currently no Rowhammer studies on RISC-V devices and it is unclear whether it is possible to compromise ... » read more

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tag: ETH Zurich

Chip Industry Week In Review

Improving Performance and Power Efficiency By Safely Eliminating Load Instruction Execution (ETH Zürich, Intel)

Chip Industry Technical Paper Roundup: July 16

Chip Industry Week In Review

Analysis Of The On-DRAM-Die Read Disturbance Mitigation Method: Per Row Activation Counting

Roadmap To Neuromorphic Computing (Collaboration of 27 Universities/Companies)

Chip Industry Week In Review

Chip Industry Technical Paper Roundup: June 18

Chip Industry Week In Review

Rowhammer Bit Flips On A High-End RISC-V CPU (ETH Zurich)

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