Chip Industry Week In Review

By The SE Staff - 10 Jul, 2026 - Comments: 0

Micron The memory maker rolled out a slew of announcements this week, including: Raised its planned U.S. investment to more than $250B through 2035, an incremental $50B above what was announced last June, with an ultimate goal of producing 40% of its DRAM in the U.S.; Planned new investments of $3B for U.S. IC supply-chain investments, including $500M in financing for GlobalWafers’ 3... » read more

Chip Industry Technical Paper Roundup: July 8

By Linda Christensen - 08 Jul, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Effect of Exchange-Correlation Functionals on Schottky Barriers at Si/Metal Interfaces NIST, University of Maryland, Johns Hopkins University AgRefactor: Self-Evolving Agentic Workflow for HLS Compatibility and Performance Carnegie Mellon University, UCLA ... » read more

Research Bits: July 6

By Jesse Allen - 06 Jul, 2026 - Comments: 0

Neural net predicts semiconductor properties Researchers from the Institute of Science Tokyo, Yokohama City University, and National Sun Yat-sen University devised a tandem neural network capable of quickly inferring key physical parameters of semiconductor materials from simple transistor measurements. The approach uses two machine learning models linked in series. The first model tries to... » read more

Chip Industry Week In Review

By The SE Staff - 03 Jul, 2026 - Comments: 0

Around the world South Korea unveiled a sweeping AI and semiconductor investment drive, planning three mega projects that tie semiconductors, physical AI/robotics, and AI data centers into a single industrial plan, with government support for regional chip clusters, packaging capacity, power, water, sites, and workforce development. Among the new investments: Samsung will spend $260B on n... » read more

Chip Industry Technical Paper Roundup: June 30

By Linda Christensen - 30 Jun, 2026 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems 🔗 The University of Tokyo, ETH Zurich, CISPA, RIKEN Recent Progress in Atomic-Scale Contr... » read more

Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna)

By Technical Paper Link - 29 Jun, 2026 - Comments: 0

Researchers from ETH Zurich, lowRISC, and University of Bologna published a technical paper titled “Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon.” This paper describes Croc, an open-source, customizable RISC-V SoC platform and teaching flow that lets students take domain-specific chip-design projects from architecture and RTL through... » read more

Chip Industry Week In Review

By The SE Staff - 26 Jun, 2026 - Comments: 0

IBM unveiled a 7Å transistor architecture that uses staggered nanosheet transistors stacked on a precisely beveled angle, almost like tiles on a roof. That allows more transistors to be crammed into a given area, boosting performance by 50% or power efficiency by up to 70%. Perhaps even more important, IBM claims a 40% improvement in SRAM scaling, which is orders of magnitude faster and lower ... » read more

Interference Risks In Processing-Using-DRAM (U. of Tokyo, ETH Zurich, CISPA, Riken)

By Technical Paper Link - 22 Jun, 2026 - Comments: 0

Researchers from The University of Tokyo, ETH Zurich, CISPA, and RIKEN published a technical paper titled “PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems.” Abstract excerpt: “We reveal PuDGhost, an interference phenomenon where a PuD operation in a given column produces erron... » read more

Chip Industry Week In Review

By The SE Staff - 19 Jun, 2026 - Comments: 0

Dealmaking Amkor inked a 10-year agreement with TSMC to provide advanced packaging and test services in Arizona, tying TSMC’s U.S. fab expansion to domestic OSAT capacity. Trump said in a post that Apple will partner with Intel on chip design and production in the U.S., marking a second reported win for the chipmaker this month. Intel Foundry will also reportedly manufacture 3 million... » read more

Chip Industry Week In Review

By The SE Staff - 12 Jun, 2026 - Comments: 0

Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

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tag: ETH Zurich

Chip Industry Week In Review

Chip Industry Technical Paper Roundup: July 8

Research Bits: July 6

Chip Industry Week In Review

Chip Industry Technical Paper Roundup: June 30

Open-Source RISC-V Platform Trains Chip Designers From RTL To Silicon (ETH Z., lowRISC, U of Bologna)

Chip Industry Week In Review

Interference Risks In Processing-Using-DRAM (U. of Tokyo, ETH Zurich, CISPA, Riken)

Chip Industry Week In Review

Chip Industry Week In Review

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