tag: ETH Zurich

Chip Industry Technical Paper Roundup: Dec. 3
By Linda Christensen - 03 Dec, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=391 /] » read more

Backpropagation Algorithm On Neuromorphic Spiking HW (U. Of Zurich, ETH Zurich, LANL)
By Technical Paper Link - 25 Nov, 2024 - Comments: 0

A new technical paper titled "The backpropagation algorithm implemented on spiking neuromorphic hardware" was published by University of Zurich, ETH Zurich, Los Alamos National Laboratory, Royal Institution, London, et al. "This study presents a neuromorphic, spiking backpropagation algorithm based on synfire-gated dynamical information coordination and processing implemented on Intel’s Lo... » read more

Chip Industry Technical Paper Roundup: Oct. 29
By Linda Christensen - 29 Oct, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=375 /] More Reading Chip Industry Week In Review Intel’s EU court win; high-NA benchmarks and new maskless litho; SiC down, GaN up; Natcast’s plan; Xiaomi’s 3nm chip; semi tax credit rules; RISC-V; lithium mine; AI-edge expansion. Technical Paper Library home » read more

Open-Source, Chiplet-Compatible RISC-V Controller
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package" was published by researchers at ETH Zurich and University of Bologna. Abstract "The increasing complexity of real-time control algorithms and the trend toward 2.5D technology necessitate the development of scalable controllers for managing the complex, integrated oper... » read more

Chip Industry Technical Paper Roundup: Oct. 14
By Linda Christensen - 14 Oct, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=367 /] More Reading Chip Industry Week In Review AI CPU chiplet platform; Intel-AMD pact; GDDR7 DRAM; AI-RFIC funding; CHIPS Act awards; NoC tiling; thermal modeling on chiplets; $900M nuclear tech and more. Technical Paper Library home » read more

PIO on Current HW Outperforms DMA Over a Range of Payload Sizes In A Number of Different Applications (ETH Zurich)
By Technical Paper Link - 11 Oct, 2024 - Comments: 0

A new technical paper titled "Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects" was published by researchers at ETH Zurich. Abstract: "Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should be based on Direct Memory Access (DMA), descriptor rings, and interrupts: DMA offloads transfers fr... » read more

Chip Industry Week In Review
By The SE Staff - 11 Oct, 2024 - Comments: 0

Imec announced a new automotive chiplet consortium to evaluate which different architectures and packaging technologies are best for automotive applications. Initial members includes Arm, ASE, Cadence, Siemens, Synopsys, Bosch, BMW, Tenstorrent, Valeo, and SiliconAuto. Imec also launched star, a global network bringing together automotive and semiconductor innovators to address technological c... » read more

Chip Industry Week In Review
By The SE Staff - 13 Sep, 2024 - Comments: 0

Infineon rolled out the world's first 300mm gallium nitride (GaN) wafer, opening the door for high-volume manufacturing of GaN-based power semiconductors. A 300mm wafer contains 2.3 times as many chips per wafer as a 200mm wafer. Fig.1: Infineon's 300mm GaN wafer. Source: Infineon The Semiconductor Industry Association released its 2024 State of the U.S. Semiconductor Industry report th... » read more

Chip Industry Technical Paper Roundup: Sept. 3
By Linda Christensen - 03 Sep, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=256 /] More ReadingTechnical Paper Library home » read more

Characterizing Three Supercomputers: Multi-GPU Interconnect Performance
By Technical Paper Link - 27 Aug, 2024 - Comments: 0

A new technical paper titled "Exploring GPU-to-GPU Communication: Insights into Supercomputer Interconnects" was published by researchers at Sapienza University of Rome, University of Trento, Vrije Universiteit Amsterdam, ETH Zurich, CINECA, University of Antwerp, IBM Research Europe, HPE Cray, and NVIDIA. Abstract "Multi-GPU nodes are increasingly common in the rapidly evolving landscape... » read more

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