Research Bits: May 19


Programmable PIC Researchers from the University of Washington designed a low-power programmable photonic integrated circuit that is electrically reconfigurable and can be mass-produced. “This optical chip could help to accelerate the prototyping cycle while reducing power consumption for applications like AI computing. Our study is also the first time someone has shown that these kinds o... » read more

Chip Industry Technical Paper Roundup: Jan. 27


New technical papers recently added to Semiconductor Engineering’s library: [table id=517 /] Find more semiconductor research papers here. » read more

Chip Industry Week In Review


TSMC is expected to reduce its Fab 14 mature-node capacity by 15% to 20% to free up resources for its advanced packaging technologies, reports Counterpoint. The foundry will likely rely on its VIS affiliate site in Singapore (operational in late 2026) and other overseas fabs to ensure continued supply for older nodes. Memory The U.S. threatened 100% tariffs on South Korean memory compan... » read more

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)


A new technical paper titled "Memory DisOrder: Memory Re-orderings as a Timerless Side-channel" was published by researchers at University of Washington, Duke University, UC Santa Cruz, Raytheon and Microsoft Research. Abstract "To improve efficiency, nearly all parallel processing units (CPUs and GPUs) implement relaxed memory models in which memory operations may be re-ordered, i.e., ex... » read more

Research Bits: Dec. 8


Iron-on circuit Researchers from Virginia Tech developed iron-on electronic circuits that can be applied to clothing. The patch uses electrically conductive liquid metal and a heat-activated adhesive to bond to fabric when heated with a hot iron. “E-textiles and wearable electronics can enable diverse applications from health care and environmental monitoring to robotics and human-machine... » read more

Chip Industry Technical Paper Roundup: Oct. 21


New technical papers recently added to Semiconductor Engineering’s library: [table id=484 /] Find more semiconductor research papers here. » read more

Heterogeneous System With Specialized HW For Disaggregated LLM Inference (Princeton Univ., Univ. of Washington)


A new technical paper titled "SPAD: Specialized Prefill and Decode Hardware for Disaggregated LLM Inference" was published by researchers at Princeton University and University of Washington. Abstract "Large Language Models (LLMs) have gained popularity in recent years, driving up the demand for inference. LLM inference is composed of two phases with distinct characteristics: a compute-boun... » read more

Chip Industry Week in Review


Podcast: imec's roadmap and a one-on-one interview with the European research house's chief strategy officer. China's Xiaomi debuted an in-house-designed 10-core mobile SoC built on a 3nm process. The company did not identify the foundry. It also announced plans to invest 50 billion yuan (~$7B) over the next decade to develop high-end smartphone chips, as part of a 200 billion yuan (~$28B) c... » read more

Chip Industry Technical Paper Roundup: May 13


New technical papers recently added to Semiconductor Engineering’s library: [table id=430 /] Find more semiconductor research papers here.   » read more

Safety Architecture and Approaches for Automotive SW And HW Including ASIL D And AI/ML (Mercedes-Benz, U. Of Washington)


A new technical paper titled "Key Safety Design Overview in AI-driven Autonomous Vehicles" was published by researchers at Mercedes-Benz Research and Development North America and University of Washington . Abstract "With the increasing presence of autonomous SAE level 3 and level 4, which incorporate artificial intelligence software, along with the complex technical challenges they present... » read more

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