USB 3.2: The Latest USB Type-C Challenge For SoC Designers

By Synopsys - 05 Sep, 2018 - Comments: 0

This white paper outlines applications that benefit from USB 3.2’s increased bandwidth, describes the latest USB 3.2 specification for USB Type-C, and explains how the latest specification affects speed using USB Type-C connectors and cables. Additionally, the white paper discusses USB 3.2 implementation, the new features of USB 3.2, and how designers can successfully integrate USB 3.2 IP in ... » read more

First Look At USB 3.2

By Eric Huang - 24 May, 2018 - Comments: 0

I’m super excited to write about and show to you the world’s first USB 3.2 demonstration. Go watch the video first and then read the rest. https://youtu.be/WPUvHeq_Sgs USB 3.2 hardware and software setup We implemented our USB 3.2 Device and Host in the HAPS-80 FPGA-Based hardware prototyping platform. The platforms use USB PHYs, which are implemented in a FinFET process node. ... » read more

The Week In Review: Design

By Jesse Allen - 06 Oct, 2017 - Comments: 0

M&A Altair acquired Runtime Design Automation. Founded in 1995, Runtime provides tools for optimizing usage of EDA tools, including flow management, job scheduling, and license utilization, as well as tools for optimizing HPC network resources. Altair's focus is on engineering simulation, with tools for HPC resource management and IoT data analytics. Terms of the deal were not disclosed. ... » read more

The Week In Review: Design

By Jesse Allen - 29 Sep, 2017 - Comments: 0

M&A Imagination will sell its MIPS business to Tallwood, a California-based venture capital firm, for $65m in cash. The sale is expected to close in October. The rest of Imagination is slated to be sold to Canyon Bridge for £550 million in cash (~$740 million), a deal dependent on the MIPS sale. The Chinese-backed investment firm has featured recently in the news for its attempted purchas... » read more

The Week In Review: Design

By Jesse Allen - 28 Jul, 2017 - Comments: 0

IP Synopsys unveiled High Bandwidth Memory 2 (HBM2) IP. The package includes PHY, controller and verification IP and supports data rates up to 2400Mb/s, 20% faster than the JEDEC standard specification. The controller supports pseudo-channel operation in either lock step or memory interleaved mode, and the PHY offers four trained power management states and fast frequency switching. Cadence... » read more

Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

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tag: USB 3.2

USB 3.2: The Latest USB Type-C Challenge For SoC Designers

First Look At USB 3.2

The Week In Review: Design

The Week In Review: Design

The Week In Review: Design