The Week In Review: Design


M&A Synopsys acquired one-time programmable non-volatile memory IP provider Kilopass. Founded in 2001, Kilopass' 1T and 2T bitcell IP supports up to 4-Mbit OTP instances in 180-nm to 7-nm process technologies. The acquisition will add to Synopsys' growing OTP NVM portfolio: last October, Synopsys acquired Sidense, another provider of the technology. Terms of the deal were not disclosed. ... » read more

Predictions: Markets And Drivers


Semiconductor Engineering received a record number of predictions this year. Some of them are just wishful thinking, but many are a lot more thoughtful and project what needs to happen for various markets or products to become successful. Those far reaching predictions may not fully happen within 2018, but we give everyone the chance to note the progress made towards their predictions at the en... » read more

Getting Serious About Chiplets


Demand for increasingly complex computation, more features, lower power, and shorter lifecycles are prompting chipmakers to examine how standardized hard IP can be used to quickly assemble systems for specific applications. The idea of using chiplets, with or without a package, has been circulating for at least a half-dozen years, and they can trace their origin back to IBM's packaging schem... » read more

Reflections On 2017: Manufacturing And Markets


People love to make predictions, and most of the time they have it easy, but at Semiconductor Engineering, we ask them to look back on the predictions they make each year and to assess how close to the mark they were. To see what they missed and what surprised them. Not everyone accepts our offer to grade themselves, but many have this year. This is the first of two parts that looks at the pred... » read more

Building In Functional Safety At The Lowest Hardware Levels Supports Autonomous Driving’s Future


Long before automotive electronic system designers chose artificial intelligence and machine learning as the path toward the future of autonomous driving’s future, it was clear that high-performance computing platforms typically found in data center systems clearly were not going to provide all the answers. Automotive system designers place more emphasis on functional safety and resilience, w... » read more

Mixing Interface Protocols


Continuous and pervasive connectivity requires devices to support multiple interface protocols, but that is creating problems at multiple levels because each protocol is based on a different set of assumptions. This is becoming significantly harder as systems become more heterogeneous and as more functions are crammed into those devices. There are more protocols that need to be supported to ... » read more

The Trouble With Models


Models are becoming more difficult to develop, integrate and utilize effectively at 10/7nm and beyond as design complexity, process variation and physical effects add to the number of variables that need to be taken into account. Modeling is a way of abstracting the complexity in various parts of the semiconductor design, and there can be dozens of models required for complex SoCs. Some are ... » read more

EDA Challenges Machine Learning


Over the past few years, [getkc id="305" kc_name="machine learning"] (ML) has evolved from an interesting new approach that allows computers to beat champions at chess and Go, into one that is touted as a panacea for almost everything. While there is clearly a lot of hype surrounding this, it appears that machine learning can produce a better outcome for many tasks in the EDA flow than even the... » read more

Big Challenges, Changes For Debug


By Ann Steffora Mutschler & Ed Sperling Debugging a chip always has been difficult, but the problem is getting worse at 7nm and 5nm. The number of corner cases is exploding as complexity rises, and some bugs are not even on anyone's radar until well after devices are already in use by end customers. An estimated 39% of verification engineering time is spent on debugging activities the... » read more

Heterogeneous Cache Coherence Requires A Common Internal Protocol


Machine learning and artificial intelligence systems are driving the need for systems-on-chip containing tens or even hundreds of heterogeneous processing cores. As these systems expand in size and complexity, it becomes too difficult to manage data flow solely through software means. An approach that simplifies software while improving performance and power consumption is to implement hardware... » read more

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