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Finding And Applying Domain Expertise In IC Analytics


Behind PowerPoint slides depicting the data inputs and outputs of a data analytics platform belies the complexity, effort, and expertise that improve fab yield. With the tsunami of data collected for semiconductor devices, fabs need engineers with domain expertise to effectively manage the data and to correctly learn from the data. Naively analyzing a data set can lead to an uninteresting an... » read more

Site-To-Site Variation In Parallel Test


From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An engineering effort is required to balance the thermo-electrical challenges that occur as you increase the number of sites to be tested, or the number of slots in a burn-in oven or system level te... » read more

Over-The-Air (OTA) Test Socket And Handler Integration Technology For 5G Mass Production Testing


This paper presents the integration of socket, measurement antenna and handler for over-the-air (OTA) testing of antenna-in-package (AiP) devices using automated test equipment (ATE) for 5G applications. The design and characteristics of sockets for performing OTA testing in the radiating near field are also discussed. The paper also describes the structure of OTA handler integration using thes... » read more

Big Payback For Combining Different Types Of Fab Data


Collecting and combining diverse data types from different manufacturing processes can play a significant role in improving semiconductor yield, quality, and reliability, but making that happen requires integrating deep domain expertise from various different process steps and sifting through huge volumes of data scattered across a global supply chain. The semiconductor manufacturing IC data... » read more

Coping With Parallel Test Site-to-Site Variation


Testing multiple devices in parallel using the same ATE results in reduced test time and lower costs, but it requires engineering finesse to make it so. Minimizing test measurement variation for each device under test (DUT) is a multi-physics problem, and it's one that is becoming more essential to resolve at each new process node and in multi-chip packages. It requires synchronization of el... » read more

High-Speed Image Processing By GPU


By using CPU and GPU together, we have increased the speed of the filter function that is often used in imaging tests. This feature is provided by the Image Processing Library (IPL) in T2000 CMOS Image Sensor Solution. Next IPE, our new image processing engine that is currently in development, is about six times faster than IPE3 (Image Processing Engine 3), an existing engine. Author: Chiezo... » read more

Making Test Transparent With Better Data


Data is critical for a variety of processes inside the fab. The challenge is getting enough consistent data from different equipment and then plugging it back into the design, manufacturing, and test flows to quickly improve the process and uncover hard-to-find defective die. Progress is being made. The inspection and test industry is on the cusp of having more dynamic ways to access the dat... » read more

Designing Chips For Test Data


Collecting data to determine the health of a chip throughout its lifecycle is becoming necessary as chips are used in more critical applications, but being able to access that data isn't always so simple. It requires moving signals through a complex, sometimes unpredictable, and often hostile environment, which is a daunting challenge under the best of conditions. There is a growing sense of... » read more

5G Chips Add Test Challenges


The advent of chips supporting millimeter-wave (mmWave) 5G signals is creating a new set of design and testing challenges. Effects that could be ignored at lower frequencies are now important. Performing high-volume test of RF chips will require much more from automated test equipment (ATE) than is required for chips operating below 6 GHz. “MmWave design is a pretty old thing,” said Y... » read more

Cleaning Up During IC Test


Test is a dirty business. It can contaminate a unit or wafer, or the test hardware, which in turn can cause problems in the field. While this has not gone unnoticed, particularly as costs rise due to increasing pin and ball density, and as more chips are bundled together in a package, the cost of dirt continues to be a focus. Cleaning recipes for test interface boards are changing, and analy... » read more

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