tag: ATE

How The Semiconductor Ecosystem Is Responding To Its Global Challenges
By Jeorge Hurtarte - 10 Sep, 2024 - Comments: 0

The semiconductor industry is changing rapidly, with government support for re-shoring capacity creating new interplay among resources in Asia, the U.S., and Europe—even as the industry develops and sustains new technologies like HBM and heterogeneous integration. Geopolitical factors such as the CHIPS (Creating Helpful Incentives to Produce Semiconductors for America) Act, the scarcity of s... » read more

Promises and Perils of Parallel Test
By Anne Meixner - 10 Sep, 2024 - Comments: 1

Testing multiple devices at the same time is not providing the equivalent reduction in overall test time due to a combination of test execution issues, the complexity of the devices being tested, and the complex tradeoffs required for parallelism. Parallel testing is now the norm — from full wafer probe DRAM testing with thousands of dies to two-site testing for complex, high-performance c... » read more

Challenges And Outlook Of ATE Testing For 2nm SoCs
By Sriharsha Vinjamury - 08 Aug, 2024 - Comments: 0

The transition to the 2nm technology node introduces unprecedented challenges in Automated Test Equipment (ATE) bring-up and manufacturability. As semiconductor devices scale down, the complexity of testing and ensuring manufacturability increases exponentially. 3nm silicon is a mastered art now, with yields hitting pretty high for even complex packaged silicon, while the transition from 3nm to... » read more

AI/ML’s Role In Design And Test Expands
By Laura Peters - 06 Aug, 2024 - Comments: 1

The role of AI and ML in test keeps growing, providing significant time and money savings that often exceed initial expectations. But it doesn't work in all cases, sometimes even disrupting well-tested process flows with questionable return on investment. One of the big attractions of AI is its ability to apply analytics to large data sets that are otherwise limited by human capabilities. In... » read more

Delivering On Power During HPC Test
By Anne Meixner - 09 Jul, 2024 - Comments: 0

The industry’s insatiable need for power in high-performance computing (HPC) is creating problems for test cells, which need to deliver very high currents at very consistent voltage levels through the power delivery network (PDN). In response, ATE, wafer probe, and contactor vendors are introducing some innovative approaches and test procedures that can ensure robust power delivery to ATE pro... » read more

Automotive Semiconductors Require Integrated Test Solution
By Toni Dircherl - 09 Jul, 2024 - Comments: 0

The automotive semiconductor test market is experiencing organic growth as chipmakers produce higher volumes of devices serving an array of automotive applications. In addition, the range of applications for automotive-grade semiconductors is evolving as the technology advances. Manufacturers of automated test equipment (ATE) are adapting to ensure their systems can handle devices ranging from ... » read more

What’s Missing In Test
By Anne Meixner - 19 Jun, 2024 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how functional test content is brought up at first silicon, and the balance between ATE and system-level testing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center... » read more

Supporting Multiple Time Domains In SoC Production Test
By Hari Mani - 14 May, 2024 - Comments: 0

Complex system-on-chip (SoC) devices make every stage of the development flow harder, and the challenges continue even after the silicon is fabricated. Automatic test equipment (ATE) screening for defective wafers and assembled chips is always challenging. Production test engineers constantly struggle to minimize expensive test pattern memory, test each wafer or chip as quickly as possible, and... » read more

The Future Of Fault Coverage In Chips
By Gregory Haley - 14 May, 2024 - Comments: 0

Heterogeneous integration and sophisticated packaging are making chips more difficult to test, necessitating more versatile and efficient testing methods to minimize the time and cost it takes for each test insertion. In the past, test costs typically were limited to about 2% of the total cost of a chip. That cost has been rising in recent years, and with chiplets, advanced packaging, and mo... » read more

Battery Management Testing: Alleviating EV Buyer Anxiety
By Thomas Koehler - 14 May, 2024 - Comments: 0

As the electric vehicle (EV) market surges towards 2040, fueled by strong consumer enthusiasm, the need to address key concerns about EV range, reliability, and battery life has become critical. Anxiety over potential range limitations, amplified by fears of scarce charging options, alongside safety worries due to media-reported battery incidents, have slowed adoption rates. Here, the semicondu... » read more

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