The Next Advanced Packages

By Mark LaPedus - 18 Jun, 2020 - Comments: 2

Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

EDA Gears Up For 3D

By Brian Bailey - 26 Aug, 2019 - Comments: 0

Semiconductor Engineering sat down to discuss changes required throughout the ecosystem to support three-dimensional (3D) chip design with Norman Chang, chief technologist for the Semiconductor Business Unit of ANSYS; John Park, product management director for IC packaging and cross-platform solutions at Cadence; John Ferguson, director of marketing for DRC applications at Mentor, a Siemens Bus... » read more

Design For Advanced Packaging

By Brian Bailey - 08 Nov, 2018 - Comments: 0

Advanced packaging techniques are viewed as either a replacement for Moore's Law scaling, or a way of augmenting it. But there is a big gap between the extensive work done to prove these devices can be manufactured with sufficient yield and the amount of attention being paid to the demands advanced packaging has on the design and verification flows. Not all advanced packaging places the same... » read more

Complexity, Reliability And Cost

By Ed Sperling - 14 Jun, 2018 - Comments: 0

Peter Schneider, director of Fraunhofer's Engineering of Adaptive Systems Division, sat down with Semiconductor Engineering to talk about future challenges in complexity, time to market and reliability issues, advanced packaging architectures, and the impact of billions of connected devices. What follows are excerpts of that discussion. SE: What is the biggest challenge you see in the semico... » read more

Blog Review: May 2

By Jesse Allen - 02 May, 2018 - Comments: 0

Arm's Greg Yeric looks towards the future of 3D ICs with a dive into transistor-level 3D, including the different proposed methods of stacking transistors, power/performance benefits, and challenges such as parasitic resistance. Mentor's Kurt Takara, Chris Kwok, Dominic Lucido, and Joe Hupcey III explain how a custom synchronizer methodology can help avoid CDC mistakes and errors in FPGA des... » read more

Blog Review: April 4

By Jesse Allen - 04 Apr, 2018 - Comments: 0

Synopsys' Richard Solomon explains PCIe's upstream and downstream component naming and why understanding the perspective is key. Mentor's Cristian Filip dives into frequency domain analysis for high data rate SerDes links and the movement toward a simpler way of channel characterization. Cadence's Paul McLellan takes a look at the history of the RISC processors and the death of microcode ... » read more

Blog Review: Dec. 2

By Jesse Allen - 02 Dec, 2015 - Comments: 0

To celebrate ARM's 25th birthday, Neil Cooper teamed up with the Science Museum in London to feature 25 people or objects that were pivotal to the creation of modern technology. This week: James Clerk Maxwell and Heinrich Hertz. Ansys' Bill Vandermark delves deep into the oceans with energy-storing balloons and up to the sky on a diamond thread in his top technology and engineering articles ... » read more

The Week In Review: Design

By Ed Sperling - 04 Apr, 2014 - Comments: 0

Tools Mentor Graphics rolled out a new platform for verification of unknown voltage levels (Xs) at the register transfer and gate levels, fusing together simulation and formal verification under one umbrella. The company says the approach will limit bugs and wasted effort caused by X-optimism and pessimism. Jasper Design Automation unveiled a new tool to verify the sequential functional equ... » read more

Plug-And-Play Test Strategy For 3D ICs

By Various Writers - 26 Feb, 2014 - Comments: 0

As the industry transitions to 3D ICs, new test strategies are being developed to meet to two 3D IC test goals: improving the pre-packaged test quality and establishing new tests between the stacked die. Solutions for 3D IC test are developing rapidly and are based on mature technologies. In this paper, we describe a test strategy for 3D ICs based on a plug-and-play architecture that allows die... » read more

Many Stresses Impact TSVs

By Ann Steffora Mutschler - 20 Feb, 2014 - Comments: 0

Too much stress in humans is typically not beneficial, and the same goes for 3D-ICs with through-silicon vias (TSVs). Stress effects here come from the fact that copper, which is the conductor of choice for the TSVs, and silicon have different coefficients of thermal expansion. “If you can imagine that a via will be etched through the silicon, copper will be deposited inside and then t... » read more

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tag: 3D ICs