中文 English

System-Level Test Methodologies Take Center Stage


Because electronic systems for all applications in end-user markets must provide the highest possible reliability to match customers’ quality expectations, semiconductor components undergo multiple tests and stress steps to screen out defects that could arise during their lifecycle. Due to new semiconductor devices’ increasing design complexity and extreme process technology, increased test... » read more

Taking Advantage Of Outsourced Test Services


The business model in today’s competitive world of commerce has shifted over recent years to “services.” Companies like Microsoft, Amazon and Google are prime success stories that have advanced the industry with business-enabling services. These economic productivity improvement services allow their customers to focus on product architecture, design and quick time to market. The service p... » read more

The Quest To Make 5G Systems Reliable


Semiconductor Engineering sat down to discuss 5G reliability with Anthony Lord, director of RF product marketing at FormFactor; Noam Brousard, system vice president at proteanTecs; Andre van de Geijn, business development manager at yieldHUB; and David Hall, head of semiconductor marketing at National Instruments. What follows are excerpts of that conversation. SE: How do we measure the reli... » read more

How To Ensure Reliability


Michael Schuldenfrei, corporate technology fellow at OptimalPlus, talks about how to measure quality, why it’s essential to understand all of the possible variables in the testing process, and why outliers are no longer considered sufficient to ensure reliability. » read more

Gaps Emerge In Automotive Test


Demands by automakers for zero defects over 18 years are colliding with real-world limitations of testing complex circuitry and interactions, and they are exposing a fundamental disconnect between mechanical and electronic expectations that could be very expensive to fix. This is especially apparent at leading-edge nodes, where much of the logic is being developed for AI systems and image se... » read more

Automotive, AI Drive Big Changes In Test


Design for test is becoming enormously more challenging at advanced nodes and in increasingly heterogeneous designs, where there may be dozens of different processing elements and memories. Historically, test was considered a necessary but rather mundane task. Much has changed over the past year or so. As systemic complexity rises, and as the role of ICs in safety-critical markets continues ... » read more

Concurrent Test


Derek Wu, senior staff applications engineer at Advantest, looks at the need for doing multiple tests at the same time as chip designs become more complex, increasingly heterogeneous, and much more difficult to test at advanced nodes. https://youtu.be/-8inbjX_af0       __________________________________ See more tech talk videos here. » read more

System-Level Testing – The New Paradigm for Semiconductor Quality Control


Covering the history and trends of system-level test for semiconductors, this solution brief discusses: The increasing complexities of testing advanced semiconductor integrated devices across a span of applications: automotive, mobile computing, wearables, and more; Semiconductor trends driving necessary shifts in testing methodologies including SiP, SoC, 3D finFETs, heterogeneous compo... » read more

System-Level Test: Where Does It Fit?


Our second C-Brief discusses where system-level test (SLT) best fits into your semiconductor test workflow. With automated testing equipment (ATE), a traditional workflow may consist of: Wafer sort (WS) Burn-in after packaging (BI) Combination of structural testing (ST) and functional testing (FT). As demands on high-volume manufacturing shift in response to wider industry and com... » read more

The Race To Zero Defects


By Jeff Dorsch and Ed Sperling Testing chips is becoming more difficult, more time-consuming, and much more critical—particularly as these chips end up in cars, industrial automation, and a variety of edge devices. Now the question is how to provide enough test coverage to ensure that chips will work as expected without slowing down the manufacturing process or driving up costs. Balanci... » read more

← Older posts