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Screening For Silent Data Errors


Engineers are beginning to understand the causes of silent data errors (SDEs) and the data center failures they cause, both of which can be reduced by increasing test coverage and boosting inspection on critical layers. Silent data errors are so named because if engineers don’t look for them, then they don’t know they exist. Unlike other kinds of faulty behaviors, these errors also can c... » read more

Emerging Technologies Are Driving System Level Test Adoption


With the size of semiconductor transistors decreasing and chip complexity increasing exponentially, semiconductor test has become essential to ensuring that only high-quality products go to market. With the introduction of more rigorous acceptable quality level (AQL) certifications, test methods must constantly evolve to meet these standards, and system level test (SLT) and traditional test... » read more

System Level Test — A Primer: White Paper


As semiconductor geometries become smaller and greater complexity is pushed into chips or packages, System Level Test (SLT) is becoming essential. Peter Reichert, System Architect for Teradyne’s System Level Test division discusses what System Level Test is, and how it can improve final product quality and reduce time to market. Click here to download the white paper. » read more

Silent Data Corruption


Defects can creep into chip manufacturing from anywhere, but the problem is getting worse at advanced nodes and in advanced packages where reduced pin access can make testing much more difficult. Ira Leventhal, vice president of U.S. Applied Research and Technology at Advantest America, talks about what’s causing these so-called silent data errors, how to find them, and why it now requires ma... » read more

Leverage Functional Interfaces For High-Speed Test Access During All Phases Of The Silicon Lifecycle


Chip testing used to be straightforward. The development team used fault simulation to select a subset of the functional tests that could detect most possible manufacturing faults. These were translated to test patterns that ran on automated test equipment (ATE) to screen out defective dies at wafer test and bad packaged chips in final test. Lots of new technology was introduced over time, incl... » read more

Trends In Testing: New Challenges Create New Opportunities


As advancements in semiconductors and microelectronics soldier ahead into emerging, even uncharted, territory, new test challenges arise. To that end, let’s look at a few key trends and challenges that are driving opportunities for innovation in the test sector. Technology convergence has been a buzzword for some time, and this trend is only going to intensify with the heightened need to m... » read more

System Level Test — A Primer


As semiconductor geometries become smaller and greater complexity is pushed into chips or packages, System Level Test (SLT) is becoming essential. SLT is testing a device under test (DUT) as it is used in the end-use system, by merely using it rather than creating test vectors, as is done with traditional automated test equipment (ATE). Tests are still written but in a different way… Pete... » read more

Semiconductor Test: Staying Ahead Of Nanodevices


In the semiconductor fabrication process, engineers continue to innovate, enabling smaller transistors and higher density circuits. The transition to finFETs allowed 7nm and 5nm processes to realize circuits of amazing density, and the progress of nanosheet transistors provides confidence in the future advancement of digital circuit cost reduction and performance improvement. As individual t... » read more

Site-To-Site Variation In Parallel Test


From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An engineering effort is required to balance the thermo-electrical challenges that occur as you increase the number of sites to be tested, or the number of slots in a burn-in oven or system level te... » read more

More Manufacturing Issues, More Testing


Douglas Lefever, CEO of Advantest America, sat down with Semiconductor Engineering to talk about changes in test, the impact of advanced packaging, and business changes that are happening across the flow. What follows are excerpts of that discussion. SE: What are the big changes ahead in test? Lefever: It's less about inflection points and more like moving from algebra to calculus in the ... » read more

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