What’s Missing In Test


Experts at the Table: Semiconductor Engineering sat down to discuss how functional test content is brought up at first silicon, and the balance between ATE and system-level testing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center... » read more

Power-Aware Revolution In Automated Test For ICs


As semiconductor devices advance in complexity and sensitivity to power fluctuations, the integration of power-aware automatic test pattern generation (ATPG) is becoming indispensable for yield and the overall functionality of a chip. Unlike traditional ATPG, which generates test patterns solely to ensure device functionality, power-aware ATPG takes it a step further by meticulously consider... » read more

The Future Of Data Analytics And Semiconductor Testing


The world is changing more rapidly than ever. With the explosion of Artificial Intelligence (AI), Machine Learning (ML) and data analytics, semiconductor manufacturers now have the opportunity to extract valuable insights from the massive amounts of data being generated throughout the silicon lifecycle. By leveraging AI algorithms and ML, semiconductor manufacturers can now optimize silicon des... » read more

Chip Industry Week In Review


President Biden will raise the tariff rate on Chinese semiconductors from 25% to 50% by 2025, among other measures to protect U.S. businesses from China’s trade practices. Also, as part of President Biden’s AI Executive Order, the Administration released steps to protect workers from AI risks, including human oversight of systems and transparency about what systems are being used. Intel ... » read more

The Future Of Fault Coverage In Chips


Heterogeneous integration and sophisticated packaging are making chips more difficult to test, necessitating more versatile and efficient testing methods to minimize the time and cost it takes for each test insertion. In the past, test costs typically were limited to about 2% of the total cost of a chip. That cost has been rising in recent years, and with chiplets, advanced packaging, and mo... » read more

The Crucial Role Of High-Performance Computing In 2024: Balancing Cost And Innovation


We live in a world where digital queries run the Information Superhighway and in turn, our lives. This means that the importance of High-Performance Computing (HPC) cannot be overstated. The technology behind this continues to be a cornerstone for advancing our world and improving productivity. To put it another way, can you imagine a day, a week, when you are not querying something? So, let... » read more

Improvement of High-Gradation DDIC Device Test Yield By T6391 High-Accuracy Measurement Solution


For DDIC (Display Driver IC) for OLED (Organic Light Emitting Diode) displays for smartphones and IT displays (tablets, laptops) and head mounted displays for AR (Augmented Reality)/VR (Virtual Reality), the output voltage will be divided into more highly-defined steps than in the past. A new per-pin digitizer and comparator module “LCD HP” was developed to measure the output voltage of the... » read more

Doing More At Functional Test


Experts at the Table: Semiconductor Engineering sat down to discuss the increasing importance of functional test, especially in high-performance computing, with Klaus-Dieter Hilliges, V93000 platform extension manager at Advantest Europe; Robert Cavagnaro, fellow in the Design Engineering Group at Intel (responsible for manufacturing and test strategy of data center products); Nitza Basoco, tec... » read more

Chip Industry Week In Review


SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Chip Industry Week In Review


Applied Materials may scale back or cancel its $4 billion new Silicon Valley R&D facility in light of the U.S. government's recent announcement to reduce funding for construction, modernization, or expansion of semiconductor research and development (R&D) facilities in the United States, according to the San Francisco Chronicle. TSMC could receive up to $6.6 billion in direct funding... » read more

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