Blog Review: Feb. 14


Siemens’ Dilan Heredia and Karen Chow explain why fast, accurate parasitic extraction (PEX) is essential to design success, especially for the 3 nm node and GAAFETs. Synopsys’ Srinivas Velivala debunks the myth that layout-versus-schematic (LVS) checking is a static step in the chip development process, and details its evolving role in modern SoCs. Cadence’s Mark Seymour digs into a... » read more

Chip Ecosystem Apprenticeships Help Close The Talent Gap


Competency-based apprenticeship programs are gaining wider acceptance across the chip industry as companies and governments look for new ways to address talent shortages, and as workers look for new skills that can span multiple industry sectors and industries. Funded in part by the CHIPS Act in the U.S. the European Chips Act, and various other nation-specific and regional programs, apprent... » read more

Adaptive Test Ramps For Data Intelligence Era


Widely available and nearly unlimited compute resources, coupled with the availability of sophisticated algorithms, are opening the door to adaptive testing. But the speed at which this testing approach is adopted will continue to vary due to persistent concerns about data sharing and the potential for IP theft and data leakage. Adaptive testing is all about making timely changes to a test p... » read more

Hidden Costs And Tradeoffs In IC Quality


Balancing reliability against cost is becoming more difficult for semiconductor test, as chip complexity increases and devices become more domain-specific. Tests need to be efficient and effective without breaking the bank, while also ensuring chips are of sufficient quality for their specific application. The problem is that every new IC device adds its own set of challenges, from smaller f... » read more

Partnership To Improve Semiconductor Quality And Yield


By Eran Rousseau (NI) and Eli Roth (Teradyne) The semiconductor industry is notorious for its high production costs and the critical importance of maintaining impeccable product quality. As technology advances and consumer expectations rise, semiconductor companies face constant pressure to meet these cost and quality goals while also delivering cutting-edge products. Traditionally, the s... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan. Cadence introduced an AI-based thermal stress and analysis platform aimed at 2.5D and 3D-ICs, and cooling for PCBs and electronic assemblies. The company also debuted a HW/SW accelerated digital twin solution for multi-physics system design and analysis, combining GPU-resident computational fluid dynamics (CFD) solvers with dedicated GPU hardwar... » read more

Blog Review: Jan. 24


Siemens' John McMillan finds that while 3D-IC capabilities are ready for mainstream, mass adoption success depends on how easily, effectively, and efficiently a solution can be delivered and points to five workflow adoption focus areas. Cadence's Andre Baguenie shows how to easily convert a logic signal to an electrical value using Verilog-AMS and the transition filter. Synopsys' Chris Cl... » read more

Glass Substrates Gain Foothold In Advanced Packages


Glass substrates are starting to gain traction in advanced packages, fueled by the potential for denser routing and higher signal performance than the organic substrates used today. There are still plenty of problems to solve before this approach becomes mainstream. While glass itself is cheap and shares some important physical similarities to silicon, there are challenges with buildup, stre... » read more

Plugging Gaps In The IC Supply Chain


Multiple touch points in manufacturing and packaging are exposing gaps in the data used to track different components, making it difficult to identify the source of issues that can affect yield and reliability, and opening the door to counterfeit or sub-standard parts. This involves more than just assigning a simple identifying code to a chip. At different points in a device's lifecycle, new... » read more

Testing ICs Faster, Sooner, And Better


The infrastructure around semiconductor testing is changing as companies build systems capable of managing big data, utilizing real-time data streams and analysis to reduce escape rates on complex IC devices. At the heart of these tooling and operational changes is the need to solve infant mortality issues faster, and to catch latent failures before they become reliability problems in the fi... » read more

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