Chip Industry Week In Review

By The SE Staff - 12 Jun, 2026 - Comments: 0

Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Why Analog And Mixed-Signal Chips Resist Adaptive Test

By Gregory Haley - 09 Jun, 2026 - Comments: 0

Key Takeaways Analog and mixed-signal test remains heavily specification-based because the measurements do not always produce a single expected result. The absence of objective coverage metrics has historically encouraged conservative test flows, which IEEE 2427-2025 begins to address. Separating device behavior from test-path variation is a prerequisite for any adaptive flow—and h... » read more

Co-Packaged Optics Testing Faces Steep Data Center Ramp

By Anne Meixner - 09 Jun, 2026 - Comments: 0

Key Takeaways: Device interface board must balance flexibility in handling with customization for different optical connectors. Test fixtures should account for DUT socketing challenges, such as warpage, coupling, and interference. Advanced data management practices will help speed yield learning. Integrating photonic and electrical ICs into co-packaged optics (CPO) requires... » read more

AI Accelerator Testing Depends On DFT Innovations

By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

The AI Server Challenge: Testing Power At Scale

By Aik-Moh Ng - 12 May, 2026 - Comments: 0

Artificial intelligence is most often framed as a story of compute advancements. Faster GPUs, denser accelerators, and advanced process nodes. But behind every AI workload, the most fundamental constraint is power. Fig. 1: AI server market. Source: Grand View Research As AI servers scale to meet data center demand, power delivery is becoming one of the most critical and complex engine... » read more

Smart Test Collides With The Data Chain

By Gregory Haley - 12 May, 2026 - Comments: 0

Key Takeaways: The promise of smart test is a data-chain problem before it is an algorithm problem. A device can pass every checkpoint and still carry a latent defect the test record never captured. As test grows more adaptive, the validity of the measurement environment matters as much as the measurement itself. For years, the test roadmap has pointed toward more adaptive f... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield

By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

Chip Industry Week in Review

By The SE Staff - 01 May, 2026 - Comments: 0

Advanced nodes and capacity The US Commerce Dept. told IC equipment makers to stop shipments to Hua Hong Group, China's No. 2 chipmaker, in order to protect America's lead, according to Reuters. Global AI competition is causing wafer and packaging shortages, but capacity increases are expected to come online later this year and in 2027 to ease the crunch, according to TrendForce. Leadi... » read more

Chip Industry Week In Review

By The SE Staff - 17 Apr, 2026 - Comments: 0

Acquisitions and business pivots Teradyne acquired Israel-based TestInsight, a semiconductor test provider with pattern conversion, validation, and virtual test capabilities. Credo plans to acquire DustPhotonics, a developer of silicon photonics PICs for optical transceivers. Molex plans to acquire Teramount, a provider of detachable, passive-alignment fiber-to-chip connectivity solu... » read more

AI data Center Providers Seek Power and Bandwidth Promise in CPO

By Teradyne - 07 Apr, 2026 - Comments: 0

Co-packaged optics (CPO), a high-speed networking technology that integrates optical components (lasers, photodetectors) directly with switch/compute chips (ASICs) in the same package, continues to show promise. Advocates of CPO maintain that it reduces power consumption by over 80% and increases bandwidth density by shortening electrical traces to millimeters. Used primarily in data cente... » read more

← Older posts

tag: Teradyne

Chip Industry Week In Review

Why Analog And Mixed-Signal Chips Resist Adaptive Test

Co-Packaged Optics Testing Faces Steep Data Center Ramp

AI Accelerator Testing Depends On DFT Innovations

The AI Server Challenge: Testing Power At Scale

Smart Test Collides With The Data Chain

HBM Shifts Testing Left To Preserve AI Chip Yield

Chip Industry Week in Review

Chip Industry Week In Review

AI data Center Providers Seek Power and Bandwidth Promise in CPO

Trending Articles

The Sub-2nm Paradox