tag: standards

New USB Standards: Benefits And Incompatibilities
By Ed Sperling - 23 Jun, 2026 - Comments: 0

Just because it's a standard doesn't mean everything will work together, and this is especially evident with conflicting USB standards. David Shin, senior product marketing manager at Cadence Design Systems, explains where incompatibilities can crop up, why it's so difficult to control the different versions, and what's behind all this confusion. » read more

1 Megawatt Racks In Data Centers
By Ed Sperling - 03 Jun, 2026 - Comments: 0

The demand for performance in an AI data center is causing a huge spike in the amount of power being consumed. Within a rack are a half-dozen SoC components housed in different types of advanced packages and connected with an assortment of blazing-fast interface IP and optical signaling. Manmeet Walia, director of product management for mixed-signal PHY IP in the Synopsys Solutions Group, talks... » read more

DFT In Automotive
By Ed Sperling - 13 May, 2026 - Comments: 0

Ensuring automotive chips are reliable, defect-free, and secure adds a whole new dimension to design for testability (DFT). Depending on the safety criticality of a system in an automobile, tests can range from key-on, once a car is started, to safety-critical features that may need to be tested every couple hundred milliseconds during operation. Lee Harrison, director of automotive IC solution... » read more

Chiplet Standards Aim For Plug-n-Play
By Bryon Moyer - 16 Apr, 2026 - Comments: 0

Key Takeaways Die-to-die chiplet standards are only the beginning. Many more standards are necessary for a chiplet marketplace. A number of such standards have either had initial versions released or are in progress. Existing work covers packaging, a system architecture, various design kits, a universal link layer, and updates to BoW. Today’s chiplets exist in silos. In a ... » read more

Verifying Scale-Up And Scale-Out In Data Centers
By Ed Sperling - 26 Feb, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

Does Your RISC-V Core Meet The Standard?
By Brian Bailey - 29 Jan, 2026 - Comments: 0

Key Takeaways Architectural conformance and implementation verification are necessary but different for RISC-V designs, yet few verification engineers have experience on the conformance side. While RISC-V enables flexibility, there is a potential for ecosystem fragmentation. It is mathematically impossible to test every instruction combination, so engineers are moving beyond just "bl... » read more

Tracing The Equipment Connectivity Journey
By Bob Reback - 09 Dec, 2025 - Comments: 0

The semiconductor industry has undergone a dramatic transformation from the early days of manual integration to today's AI-driven collaboration with equipment connectivity at the heart of this evolution. Understanding these trends is crucial for any organization looking to leverage data for improved efficiency, reliability, and competitive advantage. This blog explores milestones and emergin... » read more

3DKs: Making Headway On Chiplet Standards
By Laura Peters - 01 Dec, 2025 - Comments: 0

The chiplet model has been proven by the early adopters. Large companies that successfully developed chips at leading nodes have integrated multiple chiplets into systems, where the entire silicon cycle is performed in-house. But the industry’s long-term goal of a free and open chiplet marketplace, in which companies of any size can reap the rewards and economies of scale associated with mult... » read more

Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis
By Farhad Ahmed - 13 Nov, 2025 - Comments: 0

The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It's a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries. Questa CDC and RDC sol... » read more

Standardization Of HDMs For Hierarchical CDC And RDC Analysis
By Siemens EDA - 12 Nov, 2025 - Comments: 0

Currently hierarchical data models (HDM) must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the s... » read more

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