tag: standards

When Standards Enable Chiplets
By Brian Bailey - 30 Jul, 2025 - Comments: 0

Semiconductor Engineering sat down and discussed the need for standards to enable an ecosystem for chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute Solutions Group; and Rob Kr... » read more

Accelerating IP Reuse
By Ed Sperling - 23 Jul, 2025 - Comments: 0

Semiconductors are no longer monolithic designs developed by a single company. There is more third-party IP from different sources — as many as 1,000 different IPs in a complex SoC — and all of that needs to be integrated and work as one system, something that can require a lot of effort and time. Insaf Meliane, product management and marketing director at Arteris, talks about how the new v... » read more

Chiplet Ecosystem Slowly Emerges
By Brian Bailey - 23 Jul, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss progress and remaining challenges for designing with chiplets with Mark Kuemerle, vice president of technology for Marvell; Letizia Giuliano, vice president for product marketing and management at Alphawave Semi; Hee-Soo Lee, HSD segment lead for Keysight; Mick Posner, senior product group director for Cadence’s Compute S... » read more

Do We Have Enough Standards For An Open-Chiplet Ecosystem?
By Andy Heinig - 17 Jul, 2025 - Comments: 0

For some time now, the semiconductor industry has been discussing the development of an open chiplet ecosystem. The idea is that, rather than having monolithic systems on a chip, it should be possible to combine smaller, specialized chiplets in a modular way – ideally across different manufacturers. Doing so would promise great flexibility with much shorter development times, resulting in muc... » read more

High-Quality Data Needed To Better Utilize Fab Data Streams
By Anne Meixner - 10 Jun, 2025 - Comments: 0

Fab operations have wrestled with big data management issues for decades. Standards help, but only if sufficient attention to detail is taken during collection. Semiconductor wafer manufacturing represents one of the most complex manufacturing processes in the world. With each generation of process improvement comes more sophisticated fab equipment, new process recipes, and exponential incre... » read more

Die-to-die Interconnect Standards In Flux
By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

Analog Creates Ripples in Digital Verification
By Brian Bailey - 24 Apr, 2025 - Comments: 0

We live in an analog world, but analog has been minimized whenever possible. At some point digital and analog must come together in every electronic device, and that has long been an area where errors creep in. The Wilson Research Group and Siemens EDA functional verification study has long shown that analog and mixed signal are two of the highest causes of flaws that result in chip respins.... » read more

An Inside Look At UPF 4.0
By Barry Pangrle - 09 Apr, 2025 - Comments: 0

Energy and power efficiency are increasingly important in today’s products, and the additional complexity in new architectures to incorporate competitive power management schemes has magnified the need for newer and better methodologies for the verification, implementation, and reuse of power intent specifications. This is the focus of the new IEEE 1801-2024 Unified Power Format (UPF) 4.0 ... » read more

Advanced Packaging Moving At Breakneck Pace
By Ed Sperling And Laura Peters - 29 Jan, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss advances in packaging with Michael Kelly, vice president of Chiplets and FCBGA Integration at Amkor; William Chen, fellow at ASE; Dick Otte, CEO of Promex Industries; and Sander Roosendaal, R&D director at Synopsys Photonics Solutions. What follows are excerpts of that discussion. [Part 2 of the discussion is here.] ... » read more

How Ultra Ethernet And UALink Enable High-Performance, Scalable AI Networks
By Ron Lowman - 16 Jan, 2025 - Comments: 0

By Ron Lowman and Jon Ames AI workloads are significantly driving innovation in the interface IP market. The exponential increase in AI model parameters, doubling approximately every 4-6 months, stands in stark contrast to the slower pace of hardware advancements dictated by Moore's Law, which follows an 18-month cycle. This discrepancy demands hardware innovations to support AI workloads, c... » read more

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