Using Built-In Self-Test Hardware To Satisfy ISO 26262 Safety Requirements


The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. The ICs for safety-critical applications need to meet the ISO 26262 standard for functional safety. Among the challenges in the design flow has been aligning the metrics for design-for-test and for functional safety. This paper describes using logic built-in-self-test as b... » read more

How To Meet Functional Safety Requirements With Built-In-Self-Test


With the rapid growth in semiconductor content in today’s vehicles, IC designers need to improve their process of meeting functional safety requirements defined by the ISO 26262 standard. The ISO 26262 standard defines the levels of functional safety, known as Automotive Safety Integrity Level (ASIL), and is a mandatory part of an automotive system design process. The ASIL categories range... » read more

BiST Vs. In-Circuit Sensors


Monitoring the health of a chip post-manufacturing, including how it is aging and performing over time, is becoming much more important as ICs make their way into safety-critical applications such as the central brain in automobiles. Faced with longer lifespans and a growing body of functional safety rules, systems vendors need to be able to predict when a part will fail. But as sensing auto... » read more

Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

The Future Of Embedded Monitoring, Part 1


Shall I compare thee to a…Rolls Royce jet engine? ‘There is a new era dawning whereby deeply embedded sensing within all technology will bring about great benefit for the reliability and performance of semiconductor-based products.’ These were my words during a presentation to an industry audience in China back in September 2015. During that same presentation, somewhat to the consterna... » read more

Analog: Avoid Or Embrace?


We live in an analog world, but digital processing has proven quicker, cheaper and easier. Moving digital data around is only possible while the physics of wires can be safely abstracted away enough to provide reliable communications. As soon as a signal passes off-chip, the analog domain reasserts control for modern systems. Each of those transitions requires a data converter. The usage ... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology


This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

Automakers Changing Tactics On Reliability


Automakers are beginning to rethink how to ensure automotive electronics will remain reliable over their projected lifetimes, focusing their efforts on redundancy, more data-centric architectures and continued testing throughout the life of a vehicle. It is still too early to really know how automotive chips actually will perform over the next 15 to 20 years, especially AI logic developed at... » read more

Scan Diagnosis


Jayant D’Souza, product manager at Mentor, a Siemens Business, explains the difference between scan test and scan diagnosis, what causes values in a scan test to change, how this can be used to hone in on the actual cause of a failure in a design, and how to utilize test hardware more efficiently. » read more

Hierarchical DFT On A Flat Layout Design


The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules.  Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. But, if you need to perform the physical place and route on the full flat design, can you still take a... » read more

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