中文 English

Chip Monitoring And Test Collaborate


As on-chip monitoring becomes more prevalent in complex advanced-node ICs, it’s easy to question whether or not it conflicts with conventional silicon testing. It might even supplant such testing in the future. Or alternatively, they could interact, with each supporting the other. “On-chip monitors provide fine-grained observability into effects and issues that are otherwise difficult or... » read more

Tessent LogicBIST With Observation Scan Technology


Meeting the ISO 26262 requirements for high quality and long-term reliability mans implementing on-chip safety mechanisms with high defect coverage of IC logic. This paper describes Observation Scan Technology, a new new logic built-in-self-test (BIST) technology that improves logic BIST test quality and reduces in-system test time. Empirical results demonstrate 90% test coverage with up to 10X... » read more

Scramble For The White Space


Chipmakers are pushing to utilize more of the unused portion of a design for different functions, reducing margin in the rest of the chip to more clearly define that white space. White space typically is used to relieve back-end routing congestion before all of the silicon area is used up. But a significant amount of space still remain unused. That provides an opportunity for inserting monit... » read more

Using Built-In Self-Test Hardware To Satisfy ISO 26262 Safety Requirements


The promise of autonomous vehicles is driving profound changes in the design and testing of automotive semiconductor parts. The ICs for safety-critical applications need to meet the ISO 26262 standard for functional safety. Among the challenges in the design flow has been aligning the metrics for design-for-test and for functional safety. This paper describes using logic built-in-self-test as b... » read more

How To Meet Functional Safety Requirements With Built-In-Self-Test


With the rapid growth in semiconductor content in today’s vehicles, IC designers need to improve their process of meeting functional safety requirements defined by the ISO 26262 standard. The ISO 26262 standard defines the levels of functional safety, known as Automotive Safety Integrity Level (ASIL), and is a mandatory part of an automotive system design process. The ASIL categories range... » read more

BiST Vs. In-Circuit Sensors


Monitoring the health of a chip post-manufacturing, including how it is aging and performing over time, is becoming much more important as ICs make their way into safety-critical applications such as the central brain in automobiles. Faced with longer lifespans and a growing body of functional safety rules, systems vendors need to be able to predict when a part will fail. But as sensing auto... » read more

Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

The Future Of Embedded Monitoring, Part 1


Shall I compare thee to a…Rolls Royce jet engine? ‘There is a new era dawning whereby deeply embedded sensing within all technology will bring about great benefit for the reliability and performance of semiconductor-based products.’ These were my words during a presentation to an industry audience in China back in September 2015. During that same presentation, somewhat to the consterna... » read more

Analog: Avoid Or Embrace?


We live in an analog world, but digital processing has proven quicker, cheaper and easier. Moving digital data around is only possible while the physics of wires can be safely abstracted away enough to provide reliable communications. As soon as a signal passes off-chip, the analog domain reasserts control for modern systems. Each of those transitions requires a data converter. The usage ... » read more

Improving In-System Test With Tessent VersaPoint Test Point Technology


This paper describes a new versatile test point technology called VersaPoint, which has been developed specifically to work with designs implementing mixed EDT/LBIST methodologies to reduce EDT pattern counts and improve Logic BIST (LBIST) test coverage. VersaPoint test points can reduce compressed pattern counts 2X to 4X beyond compression alone and improve LBIST test coverage beyond what is p... » read more

← Older posts