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Testing The Stack: DFT Is Ready For 3D Devices


When existing advanced 2D designs already push the limits of design-for-test (DFT) tools, what hope do developers have of managing DFT for 3D devices? Can anyone afford the tool run time, on-chip area demand, pattern count, and test time? The answer, from an array of experts, is yes, there is a path to a scalable, affordable, and comprehensive DFT solution for 3D ICs. Well-covered strategies... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part I


The traditional processors designed for general-purpose applications struggle to meet the computing demands and power budgets of artificial intelligence (AI) or machine leaning (ML) applications. Several semiconductor design companies are now developing dedicated AI/ML accelerators that are optimized for specific workloads such that they deliver much higher processing capabilities with much low... » read more

Digital Test Bulks Up – Or Down


Large digital integrated circuits are becoming harder to test in a time- and cost-efficient manner. AI chips, in particular, have tiled architectures that are putting pressure on older testing strategies due to the volume of test vectors required. In some cases, these chips are so large that they exceed reticle size, requiring them to be stitched together. New testing efficiencies are needed... » read more

Devices Threatened By Analog Content?


As the amount of analog content in connected devices explodes, ensuring that the analog portion works properly has taken on a new level of urgency. Analog circuitry is required for interpreting the physical world and for moving data to other parts of the system, while digital circuitry is the fastest way to process it. So a sensor that gives a faulty reading in a car moving at high speed or ... » read more