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Chiplets

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A group led by DARPA, as well as Marvell, zGlue and others are pursuing chiplet technology, which is a different way of integrating multiple dies in a package or system. There are several approaches to chiplets. The basic idea is that you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme. In theory, the chiplet approach is a fast and less expensive way to assemble various types of third-party chips, such as I/Os, memory and processor cores, in a package.

With an SoC, a chip might incorporate a CPU, plus an additional 100 IP blocks on the same chip. That design is then scaled by moving to the next node, which is an expensive process. With a chiplet model, those 100 IP blocks are hardened into smaller dies or chiplets. In theory, you would have a large catalog of chiplets from various IC vendors. Then, you can mix-and-match them to build a system. Chiplets could be made at different process nodes and re-used in different designs.

Commercial Vendors
Marvell and Kandou Bus were the first to jump on the chiplet concept. They announced a deal in 2016 under which Marvell would use Kandou’s chip-to-chip interconnect technology to tie multiple chips together. Kandou is developing an ecosystem of small and midsize companies, and has agreed to give up some of its IP to others to jump-start this approach. Marvell is building a switch based on Kandou’s interconnect technology.

DARPA’s approach
In 2016, DARPA released a solicitation for bids from outside companies for its CHIPS program. The goal was (and still is) to devise a modular design and manufacturing flow for chiplets. DARPA also plans to develop a large catalog of third-party chiplets for commercial and military apps. All told, the CHIPS flow is expected to lead to a 70% reduction in design cost and turn-around times.

The CHIPS program started in 2017. The program has various types of contractors/sub-contractors—manufacturers (Intel, Northrop, Micross and UCLA); chiplet developers (Ferric, Jariet, Micron, Synopsys, and University of Michigan); and EDA suppliers (Cadence and Georgia Institute of Technology).


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