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Design Rule Checking (DRC)

A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer


Design Rule Checking (DRC) is a physical design process to determine if chip layout satisfies a number of rules as defined by the semiconductor manufacturer. Each semiconductor process will have its own set of rules and ensure sufficient margins such that normal variability in the manufacturing process will not result in chip failure.

A rule can be as simple as the minimum width of a wire and the distance between two wires.

Growth in number and complexity of physical verification rules.

The number of rules associated with the more advanced process nodes has been rapidly increasing and the sophistication of these rules rising as well. Many of these rules have spread from being single layer, to multiple layer rules.

At 45 nm and below, design constraints have become a complex, interdependent, multi-dimensional set of variables. Lithography restrictions and physical manufacturing limitations create an ever-expanding set of design requirements, leading to an explosion in rule deck size and complexity. Where simple one-dimensional checks were once sufficient, multi-dimensional checks that examine the interrelationship of multiple geometries over long ranges are now essential to ensure manufacturability. Even at mature design nodes like 90 nm and above, AMS and RF applications often have design considerations that are difficult to implement in text-based design rules. This upsurge in complexity means many desired advanced DRC checks are difficult (if not impossible) to accurately code. The increase in deck size and complexity also results in increased verification runtimes and longer debug times.

Original page contents provided by Mentor Graphics

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