How To Improve Analog Design Reuse

Existing design approaches remain inefficient, error-prone and highly customized, but that could change.


Digital circuit design is largely automated today, but most analog components still are designed manually. This may change soon. As analog design grows increasingly complex and error-prone, design teams and tool vendors are focusing on how to automate as much of the design of analog circuits as possible.

Analog design is notoriously difficult and varied. It can include anything from power management to audio sensors, and much of it highly customized. That makes it harder to develop tools because one size doesn’t fit all. In fact, one design may very different from the next, even if it’s being used in the same device.

The design of basic analog IC building blocks, such as amplifiers, comparators or switches, begins with topology selection, sizing and layout.

“For each of these steps, there are much more complex requirements for analog signal processing compared with digital,” said Uwe Eichler, analog IP engineer at Fraunhofer EAS. “That leads to a very large solution space that prevents analog circuit designers from overlooking the whole design space. It also motivates them to constantly look for design variants that better fit their requirements. Thus, even small changes in the requirements often lead to a complete redesign of a circuit, and the reuse of existing circuits or even layouts is very low.”

The result is a lot of effort to design the analog parts compared with digital parts on a per-device or per-chip-area basis. In addition, the quality of the design depends heavily on the experience of the individual designers.

“In the digital world, the complexity issue was addressed by a discretization of the design space—by predefined performance variants and regular layout shapes for each building block,” Eichler said. “Mainly, this reduction of design space complexity (in addition to the natural simplicity of digital signal processing) enabled the high automation level of the digital design flow.”

Automation approaches
Analog design always will have a hint of the black art associated with it, but there are ways to improve the predictability and reliability of those designs.

“Analog automation will never be at the same level of digital, and that is okay,” said Magdy Abadir, vice president of marketing at Helic. “We’ve come a long way, and lots of progress is being made. More analysis and optimization tools are necessary to explore the design space, and we must address the interaction between these blocks on the SoC, including phenomenon such as electromagnetic coupling. An IP must be verified in the environment it will be integrated into to investigate if there are any coupling issues.”

Another area that needs work involves analog circuit aging. This is difficult to analyze and predict with digital circuits, but it’s more difficult with analog.

There are two approaches used to analyze the reliability of custom IC designs, said Art Schaldenbrand, senior product manager at Cadence. The first is to apply the safe operating checks to the problem of reliability, which are run during standard simulations, and report if the device stress is large enough to result in “significant” changes in device characteristics. This approach has several limitations, however.

“What constitutes ‘significant’ changes in device characteristics? How do changes in device characteristics translate to changes in circuit performance? The results only provide information on whether the design passed or fails but no insight into design margin,” Schaldebrand said.

A second approach is to perform aging analysis, including simulating the stress the device experiences over its operational lifetime, calculating the device degradation due to operation, and then simulating the design at end of life—including the effect of device degradation on circuit performance. The results of the aged simulations can be checked with the same approach used for design verification. Compared to using checking, aging analysis requires additional simulation, he said.

Fraunhofer’s Eichler offered two additional approaches to analog design automation. One is to handle complexity with increased computational effort, including topology synthesis, design centering, yield optimization, and optimization-based layout synthesis. The second is to reduce complexity by re-using existing knowledge. Examples for reducing complexity include finding a tradeoff between confidence in the properties, and flexibility to adapt them to specific requirements.

“While a library of silicon-proven hard IPs provides highest confidence but no flexibility, soft IPs or so-called generators can compile a generic circuit description (containing expert design knowledge) within seconds into schematics and layouts with adjustable topology, sizing, layout, or even process technology,” Eichler said.

Fraunhofer sees a sustainable way to automate the design of analog circuits in the generator-based approach combined with optimization of specific parameters. This requires a library of circuit generators for the basic building blocks. The goal here is to reduce the complexity of the design parameter space while maintaining reasonable coverage of the performance parameter space. That also requires automating and parameterizing the generation of symbols, schematic, layouts, test benches and models. That can lead to the portability of analog designs across process technologies and in different design environments.

Second, flexibility needs to be retained to allow for new circuit development. That can be achieved by taking the following steps:

  • Using an intuitive, generic and powerful description language for hierarchical analog circuits;
  • Making the layout description based on customizable templates;
  • Establishing a customizable PDK interface to control supported devices;
  • Generate circuit data that is fully compatible with manually created data to allow partial usage and further manual adaptation of generated parts;
  • Interface to sizing and optimization engines to enable design space exploration within the generator’s parameter space;
  • Consider using larger generator libraries to select an appropriate circuit topology based on performance constraints, and
  • Establish a continuous design flow from system-level down to circuit implementation with models, representing a circuit generator’s design space.

“The reliability of the generated circuits can be controlled by an optional consideration of layout measures, such as for current density and EM,” Eichler said. “This can be supported by interfacing with existing EM analysis tools. The reliability of the design process is increased simply by the fact that important design steps are automated, leading to more reproducible results and excluding human failures for these steps.”

Still, with so many projects specifying high-performance and high-functionality requirements for mixed-signal ICs, analog is simulated along with digital designs and testbenches, said Adam Sherer, group director of marketing at Cadence.

Certain analog/mixed-signal simulation tools can be used together to assure that the analog circuits continue to function properly in the system context throughout their lifecycle.

“Since phenomenon such as NBTI increases threshold voltage and reduces mobility, it impacts timing, dynamic power, leakage circuits of digital standard cells, so engineering teams follow the analog simulations with an increasing amount of mixed-signal simulation,” Sherer said. “Among the impacts of NBTI, power is critical in IoT, mobile, and increasingly in automotive designs.”

New requirements
One of the most acute challenges designers grapple with today, amid mounting SoC complexity, is designing more reliable analog circuits more efficiently.

“Years ago, analog components were designed separately and then glued into the system at the board level, but today’s SoCs demand more and more on-board analog functionality to meet performance and cost requirements,” said Ranjit Adhikary, vice president of marketing at ClioSoft. “As such, the use of analog/mixed-signal blocks within SoCs has soared in the past decade. At the same time, design timelines have become tighter and pressures to succeed are more pronounced than ever. What’s more, design teams are now dispersed around a region or the globe, adding another layer of complexity.”

For developers of analog and mixed-signal IP blocks, there’s also the relentless challenge of having to redesign blocks for new process nodes to take advantage of improved manufacturing and more optimized design rules.

“Test chips for new process nodes from major foundries are expensive and often several variations of PDKs are required, which adds time to a given design project,” Adhikary said. Keeping track of these elements can be challenging. For foundries and PDK developers, staying on top of this complexity is also daunting. For example, which IP has been taped out using which foundry or PDK? Which customer is using which PDKs? What PDKs are these foundation libraries using?”

This kind of information is particularly critical as more analog is added into designs and as design complexity rises.

“Designers should be able to easily browse and compare analog/mixed-signal IPs for a specific PDK, check its traceability before either re-using it or modifying it for another process node,” he said. “They need quick access to the design data including the specifications, verification suite, open issues and the available knowledge-base which details what the issues and resolutions were during the project. Designers now need a single portal within the company where they can easily access all designs no matter where it is designed within the company, subject course to the approvals needed to access the data.”


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