Moore’s Law, Supply Chains And Security


The debate about the future of Moore's Law continues, while other parts of the industry look for alternatives. In between, supply chains are being pulled in multiple directions, with safety and security often in the middle. All across the semiconductor industry, significant changes are underway. Some of these have been in the works for some time. Others are new or accelerating faster than an... » read more

Auto Industry Shifts Gears On Where Data Gets Processed


In-vehicle processing is becoming a major challenge in automotive electronics due to the massive amount of data being generated by sensors — especially cameras — and the rapid response time required to avoid accidents. The initial idea that all data could be sent to the cloud for processing has been shelved, most likely permanently. In its place is a growing recognition that data needs t... » read more

Can You Afford To Waste Time On Your Next Design Project?


Let’s be honest: engineers are asked to perform miracles every day, and they almost always deliver. They are challenged to invent the future in the form of newly sophisticated, powerful and highly functional systems-on-chips and systems. On top of this, they’re required to do so with an increasingly complex array of tools and re-use increasing amounts of IP to speed time-to-market. Oh, and ... » read more

Challenges In IP Reuse


Jeff Markham, software architect at ClioSoft, explains why IP reuse is so important in advanced process node SoC chip designs, what companies need to keep track of when working with third-party IP, and how it needs to be characterized. » read more

Thoroughly Verifying Complex SoCs


The number of things that can go wrong in complex SoCs targeted at leading-edge applications is staggering, and there is no indication that verifying these chips will function as expected is going to get any easier. Heterogeneous designs developed for leading-edge applications, such as 5G, IoT, automotive and AI, are now complex systems in their own right. But they also need to work in conju... » read more

Managing Analog Designs For Successful Tapeouts


Managing analog designs beyond data management to IP reuse and beyond in order to create a collaborative platform for design management from concept-to-GDSII. Click here to read more. » read more

IP Management And Development At 5/3nm


The growing complexity of moving to new process nodes is making it much more difficult to create, manage and re-use IP. There are more rules, more data to manage, and more potential interactions as density increases, both in planar implementations and in advanced packaging. And the problems only get worse as designs move to 5nm and 3nm, and as more heterogeneous components such as accelerato... » read more

Spreadsheets In Virtuoso


The looming tape-out deadline is the nightmare that keeps most design managers up at night. Managing schedules and tracking progress is always a black art that few, if any, can master. Various project management tools and methodologies have been developed that can help, if followed diligently. However, the learning curve of the tools, or the training and overhead of the process, often result in... » read more

No Mess, No Stress


A clean and tidy working environment is often a productive environment. Imagine a desk with a lot of clutter. One may lose precious work minutes every time we go searching for a lost paper on a cluttered desk. The same is true if you are working on your designs. During the course of a design project, spirited and fast thinking design engineers run several experiments. Some of them are more s... » read more

IP’s Growing Impact On Yield And Reliability


Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

← Older posts