Spreadsheets In Virtuoso


The looming tape-out deadline is the nightmare that keeps most design managers up at night. Managing schedules and tracking progress is always a black art that few, if any, can master. Various project management tools and methodologies have been developed that can help, if followed diligently. However, the learning curve of the tools, or the training and overhead of the process, often result in... » read more

No Mess, No Stress


A clean and tidy working environment is often a productive environment. Imagine a desk with a lot of clutter. One may lose precious work minutes every time we go searching for a lost paper on a cluttered desk. The same is true if you are working on your designs. During the course of a design project, spirited and fast thinking design engineers run several experiments. Some of them are more s... » read more

IP’s Growing Impact On Yield And Reliability


Chipmakers are finding it increasingly difficult to achieve first-pass silicon with design IP sourced internally and from different IP providers, and especially with configurable IP. Utilizing poorly qualified IP and waiting for issues to appear during the design-to-verification phase just before tape-out can pose high risks for design houses and foundries alike in terms of cost and time to... » read more

Best Practices for Deploying ClioSoft SOS7 on AWS


Semiconductor integrated circuits (ICs) are at the center of a number of modern technological innovations. To keep up with the ever-increasing pace of innovation, IC design teams require robust, scalable design management (DM) solutions to enable seamless global collaboration and to increase productivity. This paper outlines the advantages of and best practices for deploying the ClioSoft SOS de... » read more

Week in Review: IoT, Security, Auto


Products/Services Rambus agreed to acquire Hillsboro, Ore.-based Northwest Logic, a purveyor of memory, PCIe, and MIPI digital controllers. The transaction is expected to close in the current quarter. Financial terms weren’t disclosed; Rambus said in a statement, “Although this transaction will not materially impact 2019 results due to the expected timing of close and acquisition accountin... » read more

Where Should Auto Sensor Data Be Processed?


Fully autonomous vehicles are coming, but not as quickly as the initial hype would suggest because there is a long list of technological issues that still need to be resolved. One of the basic problems that still needs to be solved is how to process the tremendous amount of data coming from the variety of sensors in the vehicle, including cameras, radar, LiDAR and sonar. That data is the dig... » read more

Using SOS7 Design Management Platform In Cloud


With increasing complexity of ICs, most companies need a better way to handle peak processing loads during the chip design process. Read the white paper to see how you can leverage SOS7 to manage your design data on cloud efficiently. Click here to read more. » read more

BiST Grows Up In Automotive


Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

Designing In The Cloud


Amazon AWS was launched back in 2006. Web based services such as Netflix and Expedia were early adopters, and AWS has grown rapidly, bringing in competition from Google (GCP), Microsoft (Azure) and others. It has taken a while for the design community to embrace the ‘cloud’ as some of the needs and concerns of design teams are different.  Cloud vendors have recognized this untapped market ... » read more

SOC Design & IP Management—A Must For Functional Verification


As a part of the verification flow, verification teams perform different types of simulations based on the nature of the design. The simulations include digital logic functional simulations, mixed-signal functional simulations, power-aware simulations, formal verification runs and gate-level simulations. For a signoff, all planned tests must pass in all four types of simulations. In addition t... » read more

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