tag: design rules

Gate-All-Around: TCAD and DTCO Approach To Evaluate Power and Performance (imec, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "Exploring GAA-Nanosheet, Forksheet and GAA-Forksheet Architectures: a TCAD-DTCO Study at 90 nm & 120 nm Cell Height" was published by imec, Huawei Technologies and Global TCAD Solutions. Abstract "This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power an... » read more

What Works Best For Chiplets
By Anne Meixner - 18 Apr, 2024 - Comments: 0

The semiconductor industry is preparing for the migration from proprietary chiplet-based systems to a more open chiplet ecosystem, in which chiplets fabricated by different companies of various technologies and device nodes can be integrated in a single package with acceptable yield. To make this work as expected, the chip industry will have to solve a variety of well-documented technical an... » read more

Fast, Accurate, Automated Via Insertion During Design Implementation Requires Foundry Rule Compliance
By Jimmy Tien - 10 Aug, 2023 - Comments: 0

As the scaling of silicon technology proceeds, via resistance is becoming a dominant factor in integrated circuit (IC) yield, performance, and reliability. At advanced nodes, interconnects and via dimensions decrease, while the number of metallization layers increases. To moderate the impact of via resistance on yield and reliability and reduce electromigration (EM) and voltage drop (IR) effect... » read more

How Curvilinear Mask Writing Affects Chip Design
By Ed Sperling - 12 Apr, 2023 - Comments: 0

As chips become more complex and features continue to shrink, it becomes more difficult to print shapes on photomasks. The ability to print curvilinear masks changes that equation, but not all of the pieces in the flow are automated today. Aki Fujimura, CEO of D2S, talks about what has to change, what will the impact be on design rules, and why using curvilinear shapes can shrink the manufactur... » read more

Screening For Silent Data Errors
By Anne Meixner - 10 Jan, 2023 - Comments: 0

Engineers are beginning to understand the causes of silent data errors (SDEs) and the data center failures they cause, both of which can be reduced by increasing test coverage and boosting inspection on critical layers. Silent data errors are so named because if engineers don’t look for them, then they don’t know they exist. Unlike other kinds of faulty behaviors, these errors also can c... » read more

Speed Up Early Design Rule Exploration And Physical Verification
By Siemens EDA - 21 Dec, 2022 - Comments: 0

Ensuring that early-stage IC design physical verification actually enhances IC design and verification productivity means giving engineers the ability to focus on those errors that are both valid and critical in early-stage designs. The Calibre nmDRC Recon functionality provides selective DRC of early-stage designs that focuses on real, relevant errors, ignoring rule checks that generate meanin... » read more

Mastering FOWLP And 2.5D Design Is Easier Than You Think
By Bill Acito - 22 Nov, 2022 - Comments: 0

IC packaging has come into its own, where once traditional packaging was a “necessary evil,” today’s packaging can add significant value. There is an increase in functional density and flexibility by providing a platform for heterogeneous design assembly. Where designs implemented in an SoC can become too large to yield satisfactorily and too difficult to implement on one process node, pa... » read more

Reliability Concerns Shift Left Into Chip Design
By Ann Mutschler - 22 Dec, 2021 - Comments: 1

Demand for lower defect rates and higher yields is increasing, in part because chips are now being used for safety- and mission-critical applications, and in part because it's a way of offsetting rising design and manufacturing costs. What's changed is the new emphasis on solving these problems in the initial design. In the past, defectivity and yield were considered problems for the fab. Re... » read more

Now You Can Automate Latch-Up Verification For 2.5/3D Technologies
By Dina Medhat - 12 Aug, 2021 - Comments: 0

Latch-up is modeled as a short circuit (low-impedance path) that can occur in an integrated circuit (IC). It may lead to destruction due to over-current resulting from interactions between parasitic devices (PNP and NPN). To protect against latch-up conditions, there are two key types of latch-up design rules—fundamental and advanced [1,2]. Fundamental rules are the local latch-up design r... » read more

PCB Design Rules For Wiring And Crosstalk
By Nikhil Grover - 12 Aug, 2021 - Comments: 0

Today’s electronic devices market demands miniaturized printed circuit boards (PCBs) with a multitude of high-speed functions integrated on a single board. This causes the designers to have traces routed very close to each other to optimize packaging and space. This proximity may cause unintentional coupling of electromagnetic fields, a phenomenon which we know by the name of crosstalk (see f... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy