Now You Can Automate Latch-Up Verification For 2.5/3D Technologies

Using topology-aware and voltage-aware flows to address external and mixed-voltage latch-up design rules.


Latch-up is modeled as a short circuit (low-impedance path) that can occur in an integrated circuit (IC). It may lead to destruction due to over-current resulting from interactions between parasitic devices (PNP and NPN). To protect against latch-up conditions, there are two key types of latch-up design rules—fundamental and advanced [1,2].

Fundamental rules are the local latch-up design rules that focus on physical dimension rules associated with the parasitic pnpn network. Examples of local design rules are minimum p+ to n-well spacing, minimum n+ to n-well spacing, guard ring type, minimum guard ring spacing, and minimum guard ring width.

Advanced latch-up design rules fall into two main categories: (1) external latch-up design rules, and (2) mixed voltage design rules. External rules depend on identifying the location of an external injection source; accordingly, these rules are related to separation between the injection source and victim circuit. Several studies have analyzed the effect of external latch-up and how to mitigate it in different technologies [3,4]. Mixed voltage rules, on the other hand, depend on voltage difference, which requires an additional set of rules and constraints. Various studies have analyzed the voltage effect on the latch-up design rules and the extra constraints that must be applied to the design [5,6].

Advanced latch-up design rules require knowledge of external injection sources and voltage. Applying such constrained geometrical rules using electronic design automation (EDA) tools requires the capture of this information from the design. The most common communication method currently used to identify and provide this information is through manual layout markers. However, such markers present challenges in 2D designs simply because designers sometimes misplace markers, especially when working on full chips in advanced technology nodes, where there are many marker types. Not surprisingly, then, managing layout markers methodology becomes even more difficult in 2.5D and 3D designs.

Latch-up verification in 2.5D and 3D ICs

2.5D/3D ICs have evolved into an innovative solution for many design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the BGA substrate. In 3D ICs, dies are mounted on top of each other. Communication between dies and communication with the substrate are handled by interfaces using through-silicon vias (TSVs).

Fig. 1: 2.5D versus 3D IC designs.

In 2D ICs, all pads act as IO interfaces that communicate with the outside world through the package pins. Because there are multiple dies in 2.5D and 3D integration, some pads are used to communicate signals between dies through micro-bumps, TSVs, and the interposer, and do not communicate with the outside world at all (figure 2). This key difference in 2.5D/3D ICs requires that designers differentiate between those two categories of pads by classifying them as either external IOs (connect to the outside world) or internal IOs (do not connect to the outside world).

Such classification of IOs in 2.5D/3D ICs is essential because internal IOs have low latch-up risk. This low risk allows designers to ignore verification of these IOs from a latch-up perspective and focus only on external IOs.

Fig. 2: External IOs versus internal IOs.

Challenges and methodology

Fundamental latch-up design rules can be addressed independently in 2.5/3D ICs because different dies have different local latch-up rules. These differences exist because dies are designed on different technology nodes from different foundries. Consequently, local latch-up physical verification is implemented by applying appropriate foundry design rule checks (DRC) for every die separately and analyzing problems accordingly.

The real latch-up challenges in 2.5D/3D ICs are related to the advanced latch-up design rules (i.e., external latch-up design rules, and mixed-voltage latch-up design rules). These challenges can be summarized in the following points [7]:

  • Recognizing external IOs for every die from the assembly level. This recognition is needed to implement a solution addressing external latch-up design rules requirements on each die level
  • Identifying external diffusions (latch-up injectors) inside every die topologically without using markers. External diffusion is connected to external IOs directly or indirectly through resistors, etc.
  • Assigning voltages to external IOs (or latch-up injectors) from the assembly level, and propagating these voltages to every die without using markers, to address mixed-voltage design rules requirements on the die level
  • Accounting for different technology nodes/foundries for the dies

A systematic methodology can be formulated to address these challenges and verify the latch-up design rules of 2.5D and 3D ICs [7] using an automated process. This methodology can be implemented using an electronic design automation (EDA) advanced reliability verification tool, such as the Calibre PERC reliability platform [8].

Given the layout of each die, as well as the interposer, the latch-up verification flows are based on automated differentiation between external IOs and internal IOs, without using any layout markers to drive the analysis. It is preferable to have complete layouts for dies that are free from basic design rule checking (DRC) and layout vs. schematic (LVS) errors. However, this is not a must have, because it is possible to work with partial layouts as long as they have the geometries that must be verified and the right connectivity to die ports.

Two flows are proposed: (1) a topology-aware flow for external latch-up design rules, and (2) a voltage-aware flow for mixed voltage latch-up design rules. In both flows, we start from the assembly level, as demonstrated in figure 3.

Fig. 3: Latch-up verification methodology.

The assembly level provides the complete picture for how the dies are connected with each other, so it is the right place to perform an analysis to differentiate between external IOs and internal IOs. We assume that internal IOs have low latch-up risk and don’t require latch-up verification. Therefore, the goal is to identify the external IOs, filtering out the internal IOs, to perform appropriate latch-up verification on the external IOs only.

The goal of the topology-aware latch-up flow is to address external latch-up design rules for every die. Latch-up injectors and corresponding layout geometries are automatically identified in this flow. We can then perform external latch-up DRC measurements on relevant geometries and report violations for debugging.

The goal of the voltage-aware latch-up flow is to address mixed-voltage latch-up design rules for every die.  We propagate voltages through devices from defined external ports to internal nodes in the design, enabling identification of direct/indirect connectivity of latch-up injectors. Layout geometries of the identified latch-up injectors are captured automatically. We measure the relevant geometries for mixed-voltage latch-up DRC, and report violations for debugging.

External latch-up example

Two external latch-up design rules (figure 4) are illustrated as an example of checks that can be addressed by this methodology. The design rules are:

  1. P+ diffusion connected (directly/indirectly) to an external IO pad must be surrounded by N+ guard ring
  2. N+ diffusion connected (directly/indirectly) to an external IO pad must be surrounded by P+ guard ring.

Fig. 4: External latch-up design rules.

A sample violation is demonstrated in figure 5 in one of the dies where there is a P+ diffusion connected to an external IO with no N+ guard ring protection.

Fig. 5: External latch-up violations in one of the dies.

Mixed-voltage latch-up example

Two mixed-voltage latch-up design rules (figure 6) are demonstrated as an example of checks that can be addressed by this methodology. The design rules are:

  1. P+ OD injector separation to Nwell depends on the voltage difference between them
  2. Missing voltage information results in worst case separation conditions.

Fig. 6: Mixed-voltage latch-up design rules.

A sample violation is demonstrated in figure 7 in one of the dies, where the voltage difference between an external IO and supply is (5V – 3.3V = 1.7V). According to the voltage spacing table for this die, if the voltage difference is in the range from 0 to 1.8V, the corresponding min spacing constraint is 4µm. As you can see, we have a violation because the measured spacing between the P+ OD injector and Nwell is less than the constraint.

Fig. 7: Mixed-voltage latch-up violations in one of the dies.


2.5D/3D IC verification can be challenging, but automated solutions are needed, not only to reduce verification cycles, but also to improve the quality of the design. Automated latch-up verification methodology can be used to manage the challenges of advanced latch-up verification in 2.5D/3D ICs. A topology-aware flow can address external latch-up design rules, while a voltage-aware flow can address mixed-voltage latch-up design rules. These flows are based on identification of external IOs from the assembly level, without using any special layout markers on the die level. Implementing an automated latch-up verification solution for 2.5/3D IC designs ensures accurate and consistent latch-up protection, improving the reliability and product life of these products.

For more information, download our whitepaper “2.5D/3D IC latch-up prevention: an automated verification strategy.”


  1. Voldman, Latchup. Hoboken, NJ: Wiley, 2007.
  2. H. Voldman, C. N. Perez and A. Watson, “Guard rings: Theory, experimental quantification and design,” EOS/ESD Symposium, 2005.
  3. Alvarez, W. Hartung and R. Bhandari, “ESD and Latch-up failures through triple-well in a 65nm CMOS technology,” EOS/ESD Symposium, 2018.
  4. Smedes, et al., “A DRC-based check tool for ESD layout verification,” EOS/ESD Symposium, 2009.
  5. Khazhinsky, et al., “EDA approaches in identifying latchup risks,” EOS/ESD Symposium, 2016.
  6. Oberoi, M. Khazhinsky, J. Smith and B. Moore, “Latch-up characterization and checking of a 55 nm CMOS mixed voltage design,” EOS/ESD Symposium, 2012.
  7. Medhat, M. Dessouky and D. Khalil, “Addressing Latch-up Verification Challenges of 2.5D/3D Technologies,” 2020 42nd Annual EOS/ESD Symposium (EOS/ESD), Reno, NV, USA, 2020, pp. 1-7.
  8. “Calibre PERC,” Siemens Digital Industries Software.

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