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2.5/3D IC Reliability Verification Has Come A Long Way


2.5D/3D integrated circuits (ICs) have evolved into an innovative solution for many IC design and integration challenges. As shown in figure 1, 2.5D ICs have multiple dies placed side-by-side on a passive silicon interposer. The interposer is placed on a ball grid array (BGA) organic substrate. Micro-bumps attach each die to the interposer, and flip-chip (C4) bumps attach the interposer to the ... » read more

Can We Efficiently Automate 2.5/3D IC ESD Protection Verification?


Protection against ESD events (commonly referred to as ESD robustness) is an extremely important aspect of integrated circuit (IC) design and verification, including 2.5/3D designs. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical short, or dielectric bre... » read more

Now You Can Automate Latch-Up Verification For 2.5/3D Technologies


Latch-up is modeled as a short circuit (low-impedance path) that can occur in an integrated circuit (IC). It may lead to destruction due to over-current resulting from interactions between parasitic devices (PNP and NPN). To protect against latch-up conditions, there are two key types of latch-up design rules—fundamental and advanced [1,2]. Fundamental rules are the local latch-up design r... » read more

Improving Reliability


By Dina Medhat Advanced IC designs implement complex strategies to minimize static and dynamic power. Mixed-signal designs typically require different supply voltages for the analog and digital portions of the design, and even all-digital ICs can have many power domains and operating voltages. Typically, some signal lines cross from one domain to another and special interfaces and “voltage p... » read more