tag: 3D-IC

Chiplet Interconnects Add Power And Signal Integrity Issues
By Adam Kovac - 12 Dec, 2024 - Comments: 0

The flexibility and scalability offered by chiplets make them an increasingly attractive choice over planar SoCs, but the rollout of increasingly heterogeneous assemblies adds a variety of new challenges around the processing and movement of data. Nearly all of the chiplets in use today were designed in-house by large systems companies and IDMs. Going forward, third-party chiplets will begin... » read more

ESD Verification For 2.5D And 3D-ICs
By Siemens EDA - 10 Dec, 2024 - Comments: 0

Ensuring your integrated circuit (IC) design can withstand electrostatic discharge (ESD) events without incurring damage or failure is an extremely important activity in IC circuit design and verification. While automated flows for ESD verification are well-established for regular 2D ICs, 2.5D and 3D integration presents new challenges in both ESD design and verification. The new automated ESD ... » read more

Efficient ESD Verification For 2.5/3D Automotive ICs
By Dina Medhat - 09 Dec, 2024 - Comments: 0

Protection against electrostatic discharge (ESD) events is an extremely important aspect of integrated circuit (IC) design and verification, particularly for 2.5/3D designs targeted for automotive systems. ESD events cause severe damage to ICs due to a sudden and unexpected flow of electrical current between two electrically charged objects. This current may be caused by contact, an electrical ... » read more

Critical Design Considerations For High-Bandwidth Chiplet Interconnects (TSMC)
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A new technical paper titled "High-Bandwidth Chiplet Interconnects for Advanced Packaging Technologies in AI/ML Applications: Challenges and Solutions" was published by researchers at TSMC. Abstract: "The demand for chiplet integration using 2.5D and 3D advanced packaging technologies has surged, driven by the exponential growth in computing performance required by Artificial Intelligence a... » read more

Shift Left Is The Tip Of The Iceberg
By Brian Bailey - 14 Nov, 2024 - Comments: 1

Shift left is evolving from a buzzword into a much broader shift in design methodology and EDA tooling, and while it's still early innings there is widespread agreement that it will be transformative. The semiconductor industry has gone through many changes over the past few decades. Some are obvious, but others happen because of a convergence of multiple factors that require systemic change... » read more

A Renaissance Of Innovation
By Keith Schaub - 12 Nov, 2024 - Comments: 0

Innovation in semiconductor testing plays a critical role in the advancement of the semiconductor industry, ensuring that the chips and components that power modern technology are reliable, efficient, and capable of meeting the ever-increasing demands of various applications. As semiconductors become more complex, the methods and technologies used to test them must also evolve to maintain quali... » read more

Preparing For The Multiphysics Future Of 3D ICs
By Siemens EDA - 07 Nov, 2024 - Comments: 0

3D integrated circuits (3D ICs) are emerging as a revolutionary approach to design, manufacturing and packaging in the semiconductor industry. Offering significant advantages in size, performance, power efficiency and cost, 3D ICs are poised to transform the landscape of electronic devices. However, with 3D ICs come new design and verification challenges that must be addressed to ensure success... » read more

Reliability On The Road: Multiphysics Design For Automotive 3D-ICs
By John Ferguson - 07 Nov, 2024 - Comments: 0

Anyone who has purchased a car over the past decade knows that there has been a huge increase in the amount of compute processing involved in today’s modern automotive industry. Advanced chips for diagnostics and entertainment as well as logic associated with advanced sensor technology and automated assist features have quickly become key requirements that drivers rely on every day to ensure ... » read more

Fine-Grained Functional Partitioning For Low Level SRAM Cache in 3D-IC designs (imec)
By Technical Paper Link - 27 Sep, 2024 - Comments: 0

A new technical paper titled "Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs" was published by researchers at imec. "We propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous ... » read more

Higher Density, More Data Create New Bottlenecks In AI Chips
By Adam Kovac - 12 Sep, 2024 - Comments: 0

Data movement is becoming a bigger problem at advanced nodes and in advanced packaging due to denser circuitry, more physical effects that can affect the integrity of signals or the devices themselves, and a significant increase in data from AI and machine learning. Just shrinking features in a design is no longer sufficient, given the scaling mismatch between SRAM-based L1 cache and digital... » read more

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