tag: 3D-IC

When To Move To Multi-Die Assemblies
By Ann Mutschler - 23 Dec, 2025 - Comments: 0

As chip designs become larger and more complex, especially for AI and high-performance computing workloads, it's often not feasible to fit everything onto a single planar die. But determining when to move to a multi-die assembly isn't always straightforward. Multi-die approaches have some well-documented benefits. They allow designers to split functions across different dies, which can impro... » read more

DFT Shifts Further Left
By Ed Sperling - 08 Dec, 2025 - Comments: 0

Design for test is now an essential part of all advanced-node designs, but DFT dynamics are changing with the move to multi-die assemblies. More components, including chiplets, make it imperative to analyze more data earlier. Jeff Meyer, product manager for Tessent logic test at Siemens EDA, talks about how to reduce the cost of this analysis and the time it takes to do it, how much can be shif... » read more

Calibre 3DPERC: Your Key To Robust ESD Solutions For 3D ICs
By Siemens EDA - 03 Dec, 2025 - Comments: 0

As semiconductor designs move beyond the limits of planar integration, three-dimensional (3D) IC technology introduces new challenges for ESD (electrostatic discharge) protection and verification. In this paper, author Dina Medhat explores how traditional verification methods must evolve for 3D ICs, detailing the crucial differences in pad classification, protection circuit strategies and the i... » read more

Thermal, Mechanical, And Material Stresses Grow With Die Stacking
By Ann Mutschler - 30 Oct, 2025 - Comments: 0

Managing thermal and mechanical stress in multi-die assemblies will require a detailed knowledge of how and where a device will be used, how it will be packaged, and where stresses could cause problems at any point during its expected lifetime. This includes everything from workload-dependent thermal gradients to mechanical and electrical stress, which may become more pronounced over time wi... » read more

Thermal Simulation And Optimization in 3D-IC Design (Intel, UCSB, Cadence)
By Technical Paper Link - 22 Oct, 2025 - Comments: 0

A new technical paper titled "DeepOHeat-v1: Efficient Operator Learning for Fast and Trustworthy Thermal Simulation and Optimization in 3D-IC Design" was published by researchers at Intel Corporation, University of California, Santa Barbara and Cadence. Abstract "Thermal analysis is crucial in 3D-IC design due to increased power density and complex heat dissipation paths. Although operator ... » read more

New Approaches To Limit Cyberattacks On Hardware
By Ann Mutschler - 09 Oct, 2025 - Comments: 0

The number and value of cyberattacks on semiconductors is rising, but new approaches to designing and packaging chips could put a significant dent in those figures. Semiconductor-related cybersecurity attacks have multiplied more than six times since 2022, according to a report by cyber intelligence firm CloudSEK. These attacks have cost the semiconductor industry an estimated $1.05 billion ... » read more

How 3D-IC Will Change Chip Design
By Ed Sperling - 08 Oct, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities busine... » read more

How To Cool 3D-ICs
By Ed Sperling - 01 Oct, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss how to cool 3D-ICs and what's missing from the tool chain today, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysigh... » read more

First Forays Into True 3D-IC Designs
By Ed Sperling - 25 Sep, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager... » read more

Mitigating Warpage In Multi-Chiplet Systems
By Laura Peters - 22 Sep, 2025 - Comments: 0

Warpage of dies, redistribution layers, and interposers is a growing problem in multi-chiplet packages, and it can have a dramatic impact on the behavior and reliability of these devices. Multiple factors contribute to warpage, including larger chip sizes, severe thinning of the silicon substrate, temporary bonding and debonding processes, and scaling of bump pitch and size. Each of these ca... » read more

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