How 3D-IC Will Change Chip Design

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence‘s Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysight Technologies, and Amlendu Shekhar Choubey, senior director of product management for Synopsys‘ 3D-IC compiler platform. Part 1 of this discussion is here and part 2 is here.

L-R: Keysight’s Mueth; Synopsys’ Choubey; Siemens’ Ferguson; Movellus’ Faisal; Cadence’s Posner.

SE: How different will chip design be with 3D-ICs versus 2.5D and planar SoCs?

Posner: We tend to focus on all the new challenges, but stacked multi-die also is going to impact the traditional challenges like simple verification. If you’ve got two reticle-sized dies stacked on each other, you need to verify they work with each other. And if it’s 3.5D, with horizontal and vertical stacking, simulation, validation, and all the traditional emulation and software development — that whole challenge is exponentially harder. That’s driving changes in the tools. Just to do a single SoC now is a big challenge. Now we have multiple SoCs talking to each other. A digital twin is one way to deal with this, but ultimately your RTL and your system need to be verified, so everything needs to scale.

Mueth: Yes, and if you have 10 interdependencies, now you’ve got to deal with maybe 100.

Posner: But the traditional challenges are there, as well.

Choubey: And they’re growing. Now we have to take care of heterogeneous integration. As you close timing, the number of corners will explode. How do you manage that? If you want to do timing closure across all the possible corners in a heterogeneous stacked die, it’s not going to happen. It’s not possible with today’s compute. You have to figure out how to reduce the problem so that you don’t lose anything, and you need to do it in a reasonable amount of time. All of that is coming. We have been working on these problems for some time, and we think we are making great progress on extraction, timing closure for multi-die systems and package verification. You’re not just verifying independent dies. You’re verifying the interactions between them, too.

SE: The more pieces that cross boundaries, the more you can lose in terms of performance and power. We can shorten the interconnects and put everything closer together by stacking vertically instead of horizontally across an SoC. But when you do that, you make tradeoffs. So given that everyone is looking for orders of magnitude improvements in performance at the same or less power, will there be a penalty for adding all this stuff into a package?

Faisal: The biggest and most challenging workloads that are going to bring these cloud guys the most money are chip design workloads — especially AI-driven chip design. Companies like Google suddenly want to hang out with chip designers because that is the biggest and most complex workload, and they want that business. I was at a conference where one of the top-five AI chip companies was offering a free EDA tool to everybody so they can get the workload to run their cloud. These trillion-dollar companies may come in and grab the EDA workload, and break down all the barriers and handoffs between different steps.

Choubey: Silos are the main challenge. Even when they’re going to multi-die systems, the traditional rules are still there. People who used to do digital design are doing the die, or sometimes they are doing the stacking. Then they are handing it over to someone who used to do the advanced packaging part. Those taxes are still there, because you’re still in your silo where you do something and hand it over to someone else. We need to break those silos. We have to think of it not as the integration of different design elements in one system, but as a system design. You are starting with a system definition, and you want to design that system. You partition your floor plan early and decide what it is that you actually want to do. Then, in that one place, you design all your dies and interconnects so that you have full visibility of the system. Then you’re not paying those taxes whenever you hand over the design. This is a platform that runs on a single database to keep everything in one place and take advantage of that single database and platform to make sure you don’t have silos cross the boundaries and paying a tax on performance and power each time you do. That’s going to be very important to get the benefits we want.

SE: Does this work with multiple vendors?

Ferguson: That’s where standards come in, and that’s a challenge. Standards are potentially the solution, but we’re still behind the ball on that. We’ve got some of what we need, but not enough.

SE: Right now we have basic connectivity standards, right?

Mueth: Yes, and that will help. But let’s take the case where you’re integrating high-performance electronics and digital systems. Your RF analog/mixed-signal guy designs a chip and it works great in his mind. The digital guy designs a chip and it works great in his mind. And then you integrate them together, and suddenly you’ve got noise issues that impact those chips — cross-talk, digital gates flipping in the wrong state because of noise in the ground planes. This is an integration problem. You have to deal with that at the system level, and you need a platform that can do all of this. You’re never going to have a platform that does everything, but you must have enough capability to analyze the problem at hand.

Choubey: If you’re doing an RF design, and I’m doing the digital part of that, I need to see the impact every time you make a change. I don’t want to have to ask for the latest version, then translate it and export the data so I can understand the impact. If the data is sitting there every time I run my analysis, then I have the complete data design set and I can see the impact of everything. That shortens the time-to-market and minimizes the uncertainty.

Mueth: And it’s outside the chip instead of inside models, but it has the areas you want to capture, that you’re interested in, embedded in the model. You can’t do a ROM (reduced order model) of everything. But let’s say 10 things that are important to you. You build a ROM of that chip, and then you simulate it at a system level. So now you’re at some level of abstraction, but at least you’re trying to take into account the areas that are important to you.

SE: Okay, so now you have this multi-vendor collection of dies. Who’s responsible for making sure all the pieces work together?

Posner: This leads back to standardization. You hear a lot of talk about standardization, but if you talk to the foundries, they’re not talking about that. They want a closed ecosystem because they see packaging as a differentiation. They want to add value to keep you in their channel. If you look at 2.5D horizontal, there is no convergence in the packaging technologies. Everyone has an interposer. They’re not compatible with each other. A 2D organic substrate is as close as you can get, but the vendors don’t support that. You’re on your own there. This is where it gets into the business side. If you need the performance, you’re going to make these tradeoffs. But not everyone is going to swallow the large pill that it takes to go to 3D.

Mueth: They’re afraid that if they have too much of an open ecosystem, then someone might use the whole flow. So there’s a natural tendency to build brick walls.

Ferguson: Customers don’t want the details of their chiplets, or whatever component they’ve designed, to be exposed to a third party. So you have to obfuscate it for that reason.

Posner: That also raises challenges for a chiplet marketplace. You can’t just create a die where, ‘Oh yes, you can just stack this. It will work anywhere.’

Choubey: There is always going to be some kind of customization. When you’re putting a chiplet in a system, depending on where it goes in this system and in that partition, the requirements will be different. Does it need to deliver power to something else? What is the heat profile? Hard chiplets that can be used by anyone will not be possible. It has to be a soft chiplet, and depending on where it goes, you have to be able to customize it. If you constrain the problem with a generic, hard chiplet, then you’re not going to get the optimal performance out of it. You’re restricting it too much. The idea of multi-die is that you can take advantage of a lot of things and then have the optimal solution for what you want. If you put that in a box and say, ‘No, you can’t make any changes here,’ then you are losing degrees of freedom.

SE: This becomes a different kind of problem with AI, right, because potentially it opens up too many possibilities.

Ferguson: Yes, and it’s even worse because there is more than one AI.

Faisal: There is a potential disruption coming at some point in the future from the cloud guys, because they’re very focused on open-source everything. So is there a world where that is picked up by the EDA industry and chip design, where even though the secret sauce isn’t open, a lot of stuff is? People are building fully vertical solutions, from IP to the software and beyond. But customers actually don’t like that, because sometimes they want to use that data for something else than what’s being given to them. So there’s a conflict between, ‘Give me the fully vertical solution,’ but at the same time, ‘Keep the data flow open so I can do something else with it and open up opportunities for additional optimization.

SE: We’re looking at potentially the best solution in terms of performance and power that’s ever been created with 3D-ICs, but nobody seems to be able to quite get there at the moment.

Faisal: It’s the dishwasher problem. Anybody can wash dishes, but when you install a dishwasher you need a specialist to debug it. You want the fully vertical solution, which is the dishwasher, but if it breaks nobody knows how to fix it.

SE: So are you optimistic or pessimistic about full 3D-IC?

Posner: At the moment, all the expertise for logic-on-logic or memory-on-logic has been built in-house. Will there be the kinds of flows in place that will extend 3D? As we know, from the number of prototypes, the foundries have opened the door to 3D stacked designs. They’re looking to get to the point where they can say, ‘3D stacking technology is ready for you.’ And the customers have said they are willing to prototype. I don’t think anyone has said there’s a pre-production flow or they’re going into production yet. The door has opened a little further. But it’s expensive. You have to be the cream of the crop to even play in this game.

Ferguson: We all agree that we have to be in this space. We are committed. We have no choice.

Choubey: And if you look at really high-performance compute and AI workloads over the next three years, you’ll see a majority of the designs at least starting to experiment with stacking. In that specific sector, 3D stacking is going to be the norm over the next three or four years.

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