First Forays Into True 3D-IC Designs

Experts at the Table: Semiconductor Engineering sat down to discuss initial forays into 3D-ICs and what problems early adopters will encounter, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence‘s Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities business manager at Keysight Technologies, and Amlendu Shekhar Choubey, senior director of product management for Synopsys‘ 3D-IC compiler platform. Find part 2 of this discussion here and part 3 here.

L-R: Keysight’s Mueth; Synopsys’ Choubey; Siemens EDA’s Ferguson; Movellus’ Faisal; Cadence’s Posner.

SE: Large chipmakers and systems companies are in the process of building full 3D-IC prototypes. What do you see as the big challenges?

Mueth: The problem is merging multiple technologies, including the processes used to construct these things. There’s a reliability element and a manufacturability element. And it’s not just an electrical design. The electrical part is interdependent on all the multi-physics. We do our own chiplets inside, and we’re always trying to push the performance. But 3D-IC also is about reliability and cost. Chiplets are expensive. You have to pick the right application for the job to deploy a chiplet.

Ferguson: We’re pulling it all together from a multi-physics perspective and flow implementation. Currently, a lot of focus is on thermal stresses. In particular, what we’re seeing is thermal stress not just from the traditional reliability standpoint, where you have to worry about delamination or bumps being sheared and connections being lost. There’s also the electrical impact from stresses, changing how your transistors are behaving. That is not being captured, and it’s a big part of our focus now.

Faisal: We’re going from static management of the chip to dynamic management. There used to be a data plane and a control plane, but the power management/performance management plane is emerging. That has huge implications on the power and performance of chips, especially as we go to 3D-ICs, because if I can’t probe chip number three in the stack, how do I debug it? How do I figure out the issues? That third plane is becoming increasingly important. But specifically, we’re going from static design, over-design, and then hoping something works in silicon, to actually instrumenting it and making it dynamically manageable in the field. That’s a bit more from the architectural side.

Choubey: From an EDA platform point of view, the problem is how to go from a 2D design to a 3D-IC design. How do you bring all the complexities, like multi-physics in the system and in the design, and manage them well early in the design process so that when you get to the end, you are not stuck with something that adds three to four months of turnaround time? We are used to a linear process in a 2D design, where you start with floor-planning, do your electrical and power, and then hand it over to someone in package design who will think about all the system-level stuff — how to break it out, how to do thermal. That doesn’t work with 3D-ICs. If you do ‘this’ and then ‘that,’ you’ll find issues that will throw you back nine months. And nine months is your total design turnaround time. So you need a platform that takes into account all these multi-physics effects and electrical effects, because they are interdependent. They’re not independent. And you have to zero in on which process nodes you are going to use. Are you going to use multiple process nodes or just one? Are you going to stack or go horizontal? You should have some way to understand how all these effects are going to interplay and impact your design, and then make decisions and continually refine that. You need a very strong design analysis capability so that, as your design matures, you have the best information to make these decisions and can get to a correct-by-construction design. You don’t have time to find that your thermal issues are making your timing impossible to meet, or that now you have to go back and re-floor-plan or re-partition your design into multiple chiplets. That’s not going to happen. You need a platform that brings all this together, and does that in a way that the overhead of translating the data and exporting/importing between different point tools we are used to is minimized — or eliminated in the best case.

Posner: Let’s frame this a bit more. 3D stacking isn’t going to be for everyone. It’s not applicable to all. You are not going to take on that level of complexity unless it’s delivering what you need, and that’s compute scaling, maybe compute-to-memory connectivity. Our belief is this is a problem that needs to be solved, but it’s not a problem for everyone. The solutions will be available to everyone. Multi-die gives you scalability, and it’s more applicable to different applications. 3D adds a level of complexity, multi-physics, everything we’ve talked about here. The challenge is the investment that a company needs to make. Are they going to get a return on that investment? There are many ways to solve problems, and 3D stacking is one of them. One of the main challenges is putting tools and IP in place that automate the process so that you can realize a time-to-market acceleration, because if these technologies delay you, then you’re going to miss your market window.

SE: Is it cost, complexity, or tools, or all of the above? Where do you start to tackle this?

Posner: It’s a mixture of complexity and scarcity. 2025 is going to be the year of 3D prototypes. This year is going to define how successful 3D stacking is going to be in the future. The first companies entering the 3D design world are using manual processes, early versions of tools, early versions of manufacturing, and PDKs. The outlook for 3D is going to hinge on the success of those prototypes in 2025.

Ferguson: It comes down to risk. If you’re coming from the 2D world, we have a long history for the most part. We know how to do it right. Odds of failing completely are pretty slim. When you go into the 3D space, you’re adding many new uncertainties that you don’t have to worry about in 2D. And so now you have to think about, ‘If I’m going to take this risk and I get it wrong, what’s that going to cost? What’s the impact on my business? On the other hand, if I get it right and I’m out early, how much ahead does that put me?’ You have to balance those things. There are some things, like AI, where you have to go to 3D-IC. But not everybody is going to use that if you can get away with not doing 3D-IC. If you’ve got a solution in that space that’s not 3D-IC, that’s the right thing to do. You’re going to save time and money, and you’re not going to have the same likelihood of failures, either in yield or reliability.

Faisal: I agree on the risk. However, there’s an easier first step I’m seeing in the market, which is that instead of stacking memories or logic, you solve the power delivery problem. The Qualcomm Nuvia chip has 3D capacitors embedded in the package. That brings 20% to 30% improved power efficiency. Technically, it’s 3D, but at a lower risk problem statement. It’s not going to break the design. Maybe it will affect the efficiency a bit, but it’s worth it. Graphcore has another chip where they did that. They stacked capacitors to improve the efficiency of the chip. So as an engineer, that’s probably a lower-risk way of getting to 3D and gaining the 20% to 30% efficiency, which is not the same as stacking logic or memory. You’ll see smaller companies doing that version of 3D sooner rather than later.

Choubey: Stacking may not be for everyone today, but it’s just a matter of time. There are always pioneers, either because they can invest in a technology or because they have a pressing need. And then the technology matures and becomes less risky, and it spreads. 3D stacking is mostly for AI applications right now, but people will find their own niche applications, and it will come there. It may take some time. But the technology will mature, and then we’ll see that a lot of other applications will come out of this. When place-and-route first came out, it was not for everyone. It required a heavy investment and it was uncertain. Then it matured, and now you can’t think of 2D design without automated P&R. What it will take to get there is a lot of automation and unification. The people who are going to do these designs are coming from the 2D world. They have years of experience doing 2D. We need to make 3D somewhat equivalent to 2D. It will have its own challenges and complexities, but it has to get to the point where a 2D designer can say, ‘I understand this. I know where this is going. I can minimize my risk and design something  that can deliver much more than a 2D design can. The holy grail is that someday you do P&R in a 3D system the way you are doing it in 2D right now. It’s on us, on the ecosystem, to come up with platforms and run PDKs with all the design rules and everything standardized. Then you can see the potential of multi-die solutions across industries.

Mueth: There’s a lot of risk involved because it’s costly, and yield is not there today. All of this requires the development of processes and workflows that still need to mature, as well as 3D design platforms that can deal with heterogeneous design, both from the multi-physics and electrical side. And you need to choose your app, not try to embed everything in a chip. There are some cases where you benefit from it. You have to weigh that particular use case against traditional methods. For example, internally we’re doing sub-terahertz RF. It’s really a good advantage to put that into a chiplet. But as soon as we can convert that signal to something that can be handled by a 2D design methodology, it will be much cheaper with better yield. So you only want to pick the use cases that make sense.

SE: Will the first step here be pre-integrated chiplets and modules?

Faisal: In a 3D-IC, or even a 2.5D system, all of a sudden you start getting second-, third-, and fourth-order effects like ringing and power sloshing that you can’t even imagine ahead of time. The only way to see that is to put a bunch of chiplets in a package, and then you’ll start seeing these random tones show up on your power grid. But you’ll have no idea where they came from. Well, they came from the interaction of multiple chiplets on the same substrate with a unique workload. And not only that, you may have a different workload every day of the week. Workloads are changing faster than we can turn around chips, so it becomes a very fun problem.

SE: Workloads can change by downloading software updates for one chiplet, right?

Faisal: Yes, exactly.

SE: So are we getting to the point where we’re going to be dealing with the 80/20 rule, because you can’t develop tools for an endless series of one-off designs? We need processes for tools to work, and you can’t get those processes unless you pretty much know what you’re going to be building. Is there going to be enough commonality here?

Mueth: That’s tricky, because you need to pick your application. They tend to be custom. It’s not like you can take one chiplet configuration and it’s going to be your next SoIC package that everybody uses. It’s not like that.

Posner: What we’re encountering in stacking is power density. It’s design-specific. Take the example of compute stacking. Compute is power-intensive, so that is very custom. You can’t use a standard grid array and expect to meet the power requirements of that application. That’s where thermal comes in. How efficient is the technology? What’s the picojoule/bit you’re expecting to transfer between the die? All of that plays into your signal and power integrity, thermal, and mechanical warpage.

Mueth: Standard packaging is for standard applications. But we’re not talking about standard applications here.

Posner: I personally do not see 3D going mainstream for many years because of the risk, the complexity, and the cost. What you want to do is create tools that solve very specific, big customer use cases on an application-by-application basis.