Mastering FOWLP And 2.5D Design Is Easier Than You Think

There is no longer a clear-cut delineation between silicon die design and IC packaging design.


IC packaging has come into its own, where once traditional packaging was a “necessary evil,” today’s packaging can add significant value. There is an increase in functional density and flexibility by providing a platform for heterogeneous design assembly. Where designs implemented in an SoC can become too large to yield satisfactorily and too difficult to implement on one process node, packaging now provides a platform to disaggregate the SoC die into its individual functional blocks and use the package as a substrate.

The IC packaging design tool set has matured to the point where it can address not only classic plastic, organic and ceramic packaging substrates but can also address silicon substrates driven by interposer and chiplet designs.

We have clearly entered a domain of design where what was once a clear-cut delineation between silicon die design and IC packaging design had begun to give way to an overlapping design domain where silicon foundries are generating substrates and OSATs are using silicon as substrate material; the lines between these two design domains have blurred.

For many of us, the shift in technology can be overwhelming. Do not despair; yes, there is new terminology to understand and many new design techniques to be understood and mastered, as well as a completely new design process and flow. The good news is that this can all be overcome without having to learn silicon place-and-route design tools.

As an IC package designer, we don’t have to abandon our packaging tools and learn IC place-and-route design tools to generate a silicon substrate design. In most cases, the IC packaging tools are more than adequate to design a silicon substrate, using a silicon process design kit (PDK), and in many aspects may be the preferred tool. So, IC packaging designers need not abandon their current tools; the design rules are very IC-like and the manufacturing checks will also be IC-based. But except for some very specific areas, the IC packaging layout tools can support these silicon substrates.

Fig. 1: It’s a system (image provided by CEA-Leti).

Clearly, using an IC packaging design versus an IC tool that can manage a system is important. Let’s turn our focus to how to make sure that the packaging design tool can meet all the silicon-based manufacturing requirements for implementation.

Implementing silicon design rules

Silicon substrates require specific design and manufacturing rules for their material properties and their manufacturing, just as there are specific requirements for the materials used in the various package technologies. Like die, silicon-based substrates have a specific set of design rules that are provided by the foundry or the manufacturer. These design rules govern the line width, spacing, and layer transition rules of each of the metal layers. There are rules that govern the localized density of metal on each of the layers of the design. There are rules that also govern how components are placed on the substrate, and how components are stacked and oriented within the design.

There are also specific manufacturing requirements with respect to acute angles, overlap on the same layer, and overlap layer-to-layer within the design. All these IC layout rules can be managed in the IC packaging tool with either an on-line, batch, custom or a final artwork check. Obviously, the desire is to try to pull as many of those rules forward in the design process, to have them identified early rather than finding them at the end of the design process.

With respect to the IC design PDK provided by the manufacturer, there is a level of work that must be done to convert rules the silicon foundry provides to make them available in a packaging design tool. As these design domains have historically been different, it is not a 1-to-1 match. Although many of the rules can be directly implemented in the constraint system of the IC packaging tool, some of the rules must be implemented in other functions of the tool outside of the central constraint system (e.g., governing shape parameters). Most of these rules can be leveraged at the online DRC level and the rest of them will be implemented as a batch check or an artwork check. Silicon manufactures require strict PDK compliance and verification sign-off before a design moves to mask and manufacturing. The good news is that once the conversion is done, the IC packaging PDK can be leveraged on all future designs of the same technology.

Regardless of the manufacturer of the silicon-based substrate, GDSII or OASIS will be used as the manufacturing output for manufacturing in the silicon fab, and an artwork-based checker will be used for layout verification purposes prior to generating the masks; if not by the designer, by the manufacturer. To bring those checks earlier into the design process, the artwork checker can be integrated with the design tool. Cross-probing can be leveraged with the IC packaging tool such that those issues identified in the artwork-checking tool can be cross-highlighted, verified, and corrected in the layout tool, and not just at the end of the design.

Another typical requirement of silicon and very thin organic substrate manufacturing specifications is localized metal density. This is not layer to layer, but intra-layer, localized metal density (figure 2).

Fig. 2: Density control.

Metal density has a direct impact on the process variation of etch rates and line widths on each metal layer. Due to these requirements, the packaging tool can be used to check compliance with the metal coverage and localized density rules. These density rules can be as simple as providing flooded planes in shielding areas around routing on a particular layer, to very localized density rules requiring, in some cases, perforating large via pads in the design because their density on the layer is an issue. Likewise, there’s a significant emphasis on making sure that there are no acute angles within the design. There may also be layer-to-layer coincidence requirements (e.g., void to critical signal traces). Again, the good news is the IC packaging tools can address these. It is also important that the design tool can address these requirements while not being bogged down by the size and complexity of the database.

Depending on the requirements and the PDK for the IC manufacturing technology, arcs and circles and other typical substrate-based geometries will have to be implemented in silicon. Here is a merging of the classic orthogonal rules of IC design and the any-angle traces, arcs, and circles common in packaging designs. These structures can be accommodated, either by limiting their use in the design itself (e.g., forcing orthogonal routing and using a 64-sided polygon rather than a circle) or, more commonly, having control over the way arcs and circles are converted into segmented polygons during artwork generation. There are very specific IC artwork rules that must be met with respect to the grid, acute angles, and spacing with no tolerances (figure 3). Circular and any-angle geometries can generate thousands of GDSII artwork signoff errors if not processed and generated correctly.

Fig. 3: Acute angle violation.

Not only can IC packaging design tools meet almost all silicon-based PDK manufacturing rules, they can also check additional requirements that have not historically been supported by IC design tools. The IC packaging design tools bring a wealth of additional capabilities and checks to the designer’s toolset, specifically around filled shapes, differential pair routing, and bus matching. The IC packaging designer can leverage these capabilities and checks across the interconnect of the overall system design on the silicon substrate.

There is also a wealth of interactive tools providing a better level of personal control in the implementation of the design. Digital IC design “place-and-route” tools rely heavily on batch type commands, and less interactive capabilities. IC packaging tools, relying on their PCB genealogy, provide the automation to implement the intent of the designer on the design canvas.


The IC packaging design tool set has matured to the point where it can address not only classic plastic, organic, and ceramic packaging substrates but can also address silicon substrates driven by interposer and chiplet designs. With Xpedition Substrate Integrator (xSI), Xpedition Package Designer (xPD), and Calibre3DSTACK, Siemens already offers many of the required tools to help you master FOWLP and 2.5D design. Still, in most cases system and packaging teams do not have to abandon their existing tool set to support these designs. In fact, the packaging design tool set can offer additional capabilities with respect to multi-component system design and component stacking better than an IC layout tool.

To get greater insights into the experiences of organic package substrate designers who have transitioned and mastered RDL-based FOWLP and 2.5D silicon and organic interposer design while still using (and preserving) the majority of their existing packaged design tools and skills, please check out the full paper from Siemens, An organic package designer’s guide to transitioning to FOWLP and 2.5D design.

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