Decoding GDS To Thermal Model Conversion


Driven by Moore’s Law and modern, ubiquitous computation power demand, the market will continue to demand higher chip performance. Therefore, modern chips with ever-higher power densities present critical thermal challenges. With the ever-shrinking design margins, designers must manage their thermal budget at every stage of the design, from chip to system. Now, let us shift left and start ... » read more

Hardware Trojan Detection Case Study Based on 4 Different ICs Manufactured in Progressively Smaller CMOS Process Technologies


A technical paper titled "Red Team vs. Blue Team: A Real-World Hardware Trojan Detection Case Study Across Four Modern CMOS Technology Generations" was published by researchers at Max Planck Institute for Security and Privacy, Université catholique de Louvain (Belgium), Ruhr University Bochum, and Bundeskriminalamt. "In this work, we aim to improve upon this state of the art by presenting a... » read more

Mastering FOWLP And 2.5D Design Is Easier Than You Think


IC packaging has come into its own, where once traditional packaging was a “necessary evil,” today’s packaging can add significant value. There is an increase in functional density and flexibility by providing a platform for heterogeneous design assembly. Where designs implemented in an SoC can become too large to yield satisfactorily and too difficult to implement on one process node, pa... » read more

The Quest For Curvilinear Photomasks


The semiconductor industry is making noticeable progress on the development of advanced curvilinear photomasks, a technology that has broad implications for chip designs at the most advanced nodes and the ability to manufacture those chips faster and cheaper. The question now is when will this technology move beyond its niche-oriented status and ramp up into high-volume manufacturing. For ye... » read more

Fusion Technology


Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm. To read more, click here. » read more

Managing Analog Designs For Successful Tapeouts


Managing analog designs beyond data management to IP reuse and beyond in order to create a collaborative platform for design management from concept-to-GDSII. Click here to read more. » read more

Accelerating Toshiba’s Advanced System-on-Chip (SoC) Design with Synopsys’ Fusion Compiler


Authors: Mitchy M. Mitsuyasu, Senior Specialist, Semiconductor R&D, Toshiba Electronic Device & Storage Corp.; Akira Nikaido, Director Product Marketing, Synopsys. Toshiba Electronic Devices & Storage Corporation, part of the broader Toshiba, Kawasaki Japan, has long been a technology leader in Advanced SoCs spanning multiple, key market verticals. This includes automotive, communications, I... » read more

The Problem With Post-Silicon Debug


Semiconductor engineers traditionally have focused on trying to create 'perfect' GDSII at tape-out, but factors such as hardware-software interactions, increasingly heterogeneous designs, and the introduction of AI are forcing companies to rethink that approach. In the past, chipmakers typically banked on longer product cycles and multiple iterations of silicon to identify problems. This no ... » read more

Fusion Compiler: Comprehensive RTL-to-GDSII Implementation System


The semiconductor industry is going through a renaissance period with waves of technological advancements and innovation. There has been a significant uptick in demand for silicon in recent years, driven by market sectors including automotive, artificial intelligence, cloud computing, and internet of things (IoT) that have their own unique mix of design and implementation requirements. The mobi... » read more

Synopsys’ Vision For The New Wave Of Chip Design


Learn how the recent semiconductor industry shifts are breaking the traditional RTL-to-GDSII flow, and how the new Synopsys Fusion Technology helps you cross the chasm. To read more, click here. » read more

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