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The Week In Review: Manufacturing


Chipmakers GlobalFoundries has asked European antitrust regulators to investigate TSMC over alleged unfair competition, according to a report from Reuters. Commenting on the report, a spokeswoman for GlobalFoundries said: “We are not surprised that the European Commission is looking into anti-competitive market practices and abusive conduct in the semiconductor sector. The semiconductor indu... » read more

5 Takeaways From SEMI’s SMC


At the recent Strategic Materials Conference (SMC), there were a multitude of presentations on a number of subjects. The event, sponsored by SEMI, had presentations on the IC industry, market drivers, electronic materials and other subjects. In no particular order, here are my five takeaways from SMC: Materials M&A mania Last year, the IC industry experienced a dizzying array of merger ... » read more

What Happened To ReRAM?


Resistive RAM (ReRAM), one of a handful of next-generation memories under development, is finally gaining traction after years of setbacks. Fujitsu and Panasonic are jointly ramping up a second-generation ReRAM device. In addition, Crossbar is sampling a 40nm ReRAM technology, which is being made on a foundry basis by China’s SMIC. And not to be outdone, TSMC and UMC recently put ReRAM on ... » read more

Challenges Mount For Photomasks


Semiconductor Engineering sat down to discuss photomask technologies with Naoya Hayashi, research fellow at Dai Nippon Printing (DNP); Banqiu Wu, principal member of the technical staff and chief technology officer of the Mask and TSV Etch Division at [getentity id="22817" e_name="Applied Materials"]; Weston Sousa, general manager of the Reticle Products Division at [getentity id="22876" commen... » read more

Node Warfare?


By Mark LaPedus & Ed Sperling GlobalFoundries uncorked a 12nm finFET process, which the company said will provide a 15% increase in density and more than 10% improvement in performance over the foundry's existing 14nm process. This is GlobalFoundries' second 12nm process. It announced a 12nm FD-SOI process called 12FDX last September, although it first mentioned a 12nm process back in J... » read more

Manufacturing Bits: Sept. 19


Ion implant lithography At a recent conference, the University of California at Berkeley presented more details about its efforts to develop a multiple patterning method using tilted ion implantation (TII) technology. TII is somewhat similar today’s self-aligned double patterning (SADP) processes in logic and memory. SADP and the follow-on technology, self-aligned quadruple (SAQP), enable... » read more

The Week In Review: Manufacturing


Chipmakers Toshiba has changed its mind yet again about which group will buy its prized memory unit. On June 20, Toshiba chose a Japanese government-led consortium of INCJ/DBJ, Bain Capital and South Korea’s SK Hynix. Then, Toshiba changed its mind and selected a similar group with Western Digital (WDC), leaving SK Hynix on the outside looking in. This week, Toshiba signed a deal with a ... » read more

Manufacturing Bits: Sept. 12


Failure analysis for 2.5D/3D chips Imec has developed a new failure analysis method to localize interconnection failures in 2.5D/3D stack die with through-silicon vias (TSVs). This technique is called LICA, which stands for light-induced capacitance alteration. It addresses the reliability issues for 2.5D/3D devices in a non-destructive and cost-effective manner at the wafer level. For s... » read more

Survey: Optimism Grows for EUV


The optimism is growing for extreme ultraviolet (EUV) lithography in the market, according to a pair of new surveys released by the eBeam Initiative, which also revealed some new and surprising data about mask writing tools and other photomask technology. In one of the surveys from the [getentity id="22818" e_name="eBeam Initiative"], respondents revealed that they are more optimistic than e... » read more

Inside Panel-Level Fan-Out Technology


Semiconductor Engineering sat down to discuss panel-level fan-out packaging technology with Tanja Braun, deputy group manager at the Fraunhofer Institute for Reliability and Microintegration IZM, and Michael Töpper, business development manager at Fraunhofer IZM. Braun is responsible for the Panel Level Packaging Consortium at Fraunhofer IZM, as well as the group manager for assembly and encap... » read more

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