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Paving The Way To Chiplets

Different interconnect standards and packaging options being readied for mass chiplet adoption.

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The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages.

New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet model forward, although challenges and gaps remain with the technology.

With this methodology, a packaging house may have a menu of modular dies or chiplets with different functions and process nodes in a library. Then, chip customers can select any of these chiplets and have them assembled in an advanced package, resulting in a new, complex chip design as an alternative to a system-on-a-chip (SoC).

The chiplet model has been proven to work by companies such as Intel, AMD, and Marvell, which design their own chiplets and interconnects. Now, the rest of the industry is exploring chiplets, largely because scaling is becoming too difficult and costly for many, and the power and performance benefits of moving to new nodes are shrinking. Advanced packaging provides a cost-effective way to combine chips at different technology nodes, and chiplets offer a solution to increasing interconnect RC delays. They also hold the promise of developing complex chips more quickly, and they can be customized for specific markets and applications.

Traditionally, to develop a complex IC product, vendors designed a chip that integrated all functions on the same die. At each succeeding generation, the number of functions per die increased dramatically. At the latest nodes, 7nm and 5nm, cost and complexity skyrocketed. (A node refers to a specific process and its design rules.)

“The cost of designing new silicon nodes is going up,” said Mudasir Ahmad, an advanced technology development engineer at Google, in a recent presentation. “Just to give you a scale, the cost of doing a 5nm chip these days is more or almost the same as the cost of doing 10nm and 7nm chips combined. It’s extremely expensive.”

While the traditional approach remains an option for new designs, chiplets provide customers with an alternative solution. But like any new technology, chiplet integration is not simple. For now, chiplet-based designs are exclusively used in higher-end products rather than everyday designs. Even then, it takes several pieces to bring up a chiplet-based model. Only a few large companies have the needed in-house expertise and capability, much of which is proprietary.

This has limited the adoption of the chiplet-based approach to a select few. But now, work is underway to make chiplet-based designs more accessible. These efforts include:

  • ASE, AMD, Arm, Google, Intel, Meta, Microsoft, Qualcomm, Samsung, and TSMC formed a new chiplet consortium. The group released a new, open die-to-die interconnect specification, enabling chiplets to communicate with one another in a package.
  • The Open Domain-Specific Architecture (ODSA) Sub-Project is putting the finishing touches on a similar technology. ODSA also just released a new cost analysis tool, which helps determine whether a given chiplet-based design is feasible.
  • Several packaging houses are developing the manufacturing technologies to put chiplet-based designs into production.

Chiplets are challenging
Generally, to develop a chiplet-based design, the first step is to define the product. Then, a proposed chiplet-based design requires several pieces, such as a product architecture, known-good die (KGD), and die-to-die interconnects. It also requires a sound manufacturing strategy.

KGD are the dies or chiplets used in a design. Die-to-die interconnects allow chiplets to communicate with one another in the design. By developing or sourcing these pieces, chip customers can develop a chiplet-based design, at least on paper.

But the big question is whether the design is feasible or cost-effective. This could be a major stumbling block, preventing risk-averse chip customers from considering chiplets.

To help customers here, ODSA has released a cost analysis software tool that includes a spreadsheet of all of the possible components and costs involved in developing chiplet-based designs.

“There’s no generic rule that says you should always do chiplets or you shouldn’t. It all depends on that specific application,” Google’s Ahmad said. “We need a model that can be used for each application to provide feedback. [With the spreadsheet, chip customers] can input data into it with a common framework. Then they can try to understand if it makes sense for them to do a chiplet for a particular application.”

Cost isn’t the only factor. Engineers must also look at the challenges with chiplets. According to Ahmad, here are some of those challenges:

  • Scrap cost: If one chiplet fails in one or more of the final designs, the device may get scrapped. That increases scrap costs.
  • Test: To minimize scrap losses, the design requires more test coverage.
  • Yield: Package complexity may impact overall yield.
  • Performance: Moving signals from one die to another may degrade the performance of the product.

The business model is another challenge. “If you have different suppliers providing different parts and you are putting them all together into a package, who’s responsible for what? Who takes the liability for failures?” Ahmad asked.

Architectures, KGD, interconnects
The cost and technical challenges are just part of the equation with chiplets. Customers must also define the product and select an architecture for the design.

There are many options here. Customers could incorporate the dies in an existing advanced package or a new architecture.

Fan-out is one option. In one example of a fan-out package, a DRAM die is stacked on a logic chip in the package.

Used in high-end systems, 2.5D is another option. In 2.5D, dies are stacked on an interposer, or connected side-to-side. The interposer incorporates through-silicon vias (TSVs), which provide an electrical connection from the dies to the board. In one example, an ASIC and high-bandwidth memory (HBM) are placed side-by-side on the interposer. An HBM is a DRAM memory stack.

Another option is to incorporate chiplets in a new 3D architecture. For example, Intel is developing a GPU architecture, code-named Ponte Vecchio. This device incorporates 47 tiles or chiplets at five different process nodes in one package.

Fig. 1: Different options for high-performance compute packaging, interposer-based 2.5D vs. Fan-Out Chip on Substrate (FOCoS). Source: ASE

Fig. 1: Different options for high-performance compute packaging, interposer-based 2.5D vs. Fan-Out Chip on Substrate (FOCoS). Source: ASE

 

Fig. 2: More examples of 2.5D packages, high-density fan-out (HDFO), packages with bridges, and chiplets. Source: Amkor

Fig. 2: More examples of 2.5D packages, high-density fan-out (HDFO), packages with bridges, and chiplets. Source: Amkor

Any chiplet-based architecture requires known good die, which is a die that meets a given specification. Without KGD, the package may suffer from low yield or will fail in the field.

“We receive bare dies and we put them into the package to deliver a product with functionality,” said Lihong Cao, director of engineering and technical marketing at ASE, at a recent event. “In regards to KGD, we want to have it fully tested with good functionality. We want it to be 100%.”

That’s not the only challenge. In a package, some dies are stacked, while others reside elsewhere. So you need a way to connect one die to another using die-to-die interconnects.

Today’s chiplet-like designs connect the dies using proprietary interconnects, which limits the adoption of the technology. “The biggest roadblock to chiplets becoming the new IP is standardization,” said Richard Otte, president and CEO of Promex, the parent company of QP Technologies. “Standard/common communication interfaces between chiplets must be established for this to be viable across multiple packaging providers.”

The good news is that several organizations are working on open die-to-die interconnect standards for chiplets. At present there are several competing technologies, and it’s not clear which will win or how they might be combined.

ODSA is readying one die-to-die interconnect technology called Bunch of Wires (BoW). Other die-to-die technologies include the Advanced Interface Bus (AIB), CEI-112G-XSR, and OpenHBI.

In the latest effort, a new chiplet consortium backed by Intel, Samsung, TSMC and others have released UCIe, a specification that covers the die-to-die I/O physical layer, die-to-die protocols, and the software stack.

All of the above specifications define the standard interconnect between chiplets within a package, but they are all different. “Both UCIe and BoW are open specifications that define the interconnect between chiplets within a package and enable an open chiplet ecosystem. But they are not the same as how to define the layers and optimize the applications differently,” ASE’s Cao said.

As it turns out, no one interconnect technology can meet all needs. Engineers will select an option that meets the requirements for a given application. “There is an area of overlapped subsets between the various standards,” said Choon Lee, CTO at JCET. “So sticking to one standard may not have a significant meaning. In general, the functional blocks of chiplets are defined by the device makers. They know how to optimize the interconnections between the chiplets.”

Chiplet stacking/bonding options
Once the chiplet architecture, KGDs, and interconnects are defined, the next step is to determine whether it makes sense to put the product into production.

As before, a package or chiplet-like design could be manufactured and assembled at a foundry, memory maker, or OSAT. Some, but not all, foundries and memory makers have their own internal packaging assembly operations.

Each vendor has different capabilities. And each one is developing one or more different ways to assemble, stack and bond different chiplets together in a package. Among the advanced bonding techniques are thermocompression, laser-assisted, and copper hybrid bonding.

Both thermocompression bonding (TCB) and laser-assisted bonding (LAB) utilize traditional flip-chip processes with copper microbumps. In this process, copper bumps are formed on a die and then the device is bonded to another structure using a flip-chip bonder, LAB or TCB. In contrast, copper hybrid bonding stacks and connects dies using copper interconnects, not traditional bumps.

Traditional flip-chip processes are used to make several package types. One type, called ball grid array (BGA), is used for several chip applications.

To make BGA packages, the process starts by manufacturing chips on a wafer in a fab. Then, tiny copper bumps based on solder materials are formed on one side of a wafer. The bumps consist of a copper pillars with a thin nickel diffusion barrier and a tin-silver solder cap.

Copper bumps connect one die to another or to a substrate in the package. Those bumps provide small, fast electrical connections between different structures. Making copper bumps is a well-known process.

Fig. 3: Microbump process flow. Source: John Lau, Unimicron

Fig. 3: Microbump process flow. Source: John Lau, Unimicron

Once the bumps are made on the wafer, the chips are diced. Then, the device undergoes a traditional flip-chip process.

First, a die is placed in a flip-chip bonder. Generally, flip-chip bonders are used to stack and bond dies at 300μm to 50μm bump pitches. Today’s bump pitches extend to 40µm and below. (Pitch refers to the space between adjacent bumps on the die.)

“A lot of flip-chip devices don’t require fine pitches,” said Bob Chylak, CTO of Kulicke & Soffa (K&S). “The flip-chip bonder takes the chip, dips the solder balls into a flux, and places them on a PCB.”

This process is repeated several times. Eventually, several dies are placed on the PCB, sometimes called a die substrate. Then, it undergoes a mass reflow process. “The PCB goes through a reflow oven, and the reflow oven melts the solder and then solidifies it,” Chylak said.

Following the reflow process, the dies on the PCB undergo a cleaning step. Then, a system injects a mold compound over each bumped die on the PCB. “[This seals] all the components, protecting the die and bumps inside the device,” said Wan-Chun Chuang, a researcher at National Sun Yat-sen University, in a paper.

Then, larger C4 solder balls are implanted underneath the base PCB substrate. Finally, the dies on the PCB are diced, creating individual BGA packages with dies inside each unit.

The industry requires a different solution for advanced packages using the most advanced copper microbumps involving 40μm pitches and tighter. But it’s challenging to use traditional flip-chip bonders at these pitches. For finer pitches, some packaging houses use TCB for die stacking and bonding applications at 40μm to 10μm bump pitches.

Generally, TCB is used for chip stacking and bonding for 2.5D/3D packages.

Fig. 4: 2.5D/3D system architecture. Copper microbumps connect interposers and base dies. Source: Rambus

Fig. 4: 2.5D/3D system architecture. Copper microbumps connect interposers and base dies. Source: Rambus

In the TCB process, tiny copper bumps are formed on the dies using a traditional bump process. In this case, though, the bumps are smaller with finer pitches. Then, rather than using a traditional flip-chip bonder, packaging houses use a TCB tool.

“Instead of heating the entire circuit board and all the chips on it, the thermocompression bonder grabs the die, dips it in flux just like a regular flip-chip, and places it on the PCB,” K&S’ Chylak said. “There’s a heater in the bond head. That heats up past the melting point of solder holding the chip in place. Then it cools down so that the solder solidifies.”

Meanwhile, LAB, a lesser-known option, is also viable. In the LAB process, tiny copper bumps are formed on the die using a traditional bump process.

Then, the bumped dies and a substrate are placed in a LAB tool. The system aligns and bonds the dies to the substrate using heat generated by a laser.

“(LAB equipment) features an infrared laser source (980nm wavelength) and an optical system (homogenizer) that can produce a sharp and homogeneous laser beam capable of selectively heating up a target area at an extremely high ramp-up speed. The heating mechanism of the LAB process is based on the absorption of a photon’s energy by a material, and on the subsequent dissipation of this energy to its atoms,” said Wagno Alves Braganca, a senior research and development engineer at JCET, in a paper. Others contributed to the work.

In a LAB system, the bonding process occurs in less than a second with low thermal stress. LAB is faster than TCB, but it requires specialized equipment from select vendors.

Amkor and JCET are developing LAB. The technology has been in production since about 2019. “LAB has been in production for high-performance computing applications, where bump non-wet or cracking due to warpage or residual stress may be critical,” JCET’s Lee said.

OSATs hope to push LAB to 10μm pitches or so. “We have demonstrated down to 10μm pitches using copper lead-free bumps and our laser-assisted bonding approach. We have products qualifying in the 20μm pitch arena. These are all chip-on-wafer, and are mostly specialty sensors,” said Michael Kelly, vice president of advanced packaging development and integration at Amkor.

Hybrid bonding
Both TCB and LAB extend to 10μm bump pitches. Beyond that, the industry requires a new solution, namely copper hybrid bonding. Here, the idea is to stack and connect dies directly using fine-pitch copper connections, not traditional microbumps.

Copper hybrid bonding isn’t new. In 2005, Ziptronix introduced a technology called low-temperature direct bond interconnect (DBI), considered the first version of copper hybrid bonding. (In 2015, Tessera acquired Ziptronix. In 2017, Tessera changed its name to Xperi.)

In 2015, Sony licensed DBI and implemented the technology for its CMOS image sensor lines. Other image sensor vendors also licensed DBI.

For CMOS image sensors, vendors follow a wafer-to-wafer hybrid bonding process flow. First, two different wafers are processed in a fab. The first wafer consists of a multitude of processor dies. The second wafer consists of a multitude of pixel array dies.

The goal is to stack each pixel array die on top of each processor die. For this, the two wafers are inserted in a wafer bonder. The bonder aligns each die and joins them using a two-step bonding process. First it forms the dielectric-to-dielectric bond, followed by the metal-to-metal connection. Finally, the dies on the wafer are diced and packaged, resulting in image sensors.

Using Xperi’s DBI process, Sony, and OmniVision are in production with CMOS image sensors at 3.1μm and 3.9μm pitches, respectively.

Now, the industry is developing copper hybrid bonding for 3D chip and packaging applications. AMD, Graphcore, and YMTC have announced products using hybrid bonding from various vendors. Others are in R&D.

In packaging, hybrid bonding is used for both wafer-to-wafer and die-to-wafer bonding. In die-to-wafer, two wafers with chips are processed in the fab. Then, the chips on the first wafer are diced and bonded to the second wafer using hybrid bonding.

Fig. 5: Xperi’s die-to-wafer hybrid bonding flow. Source: Xperi

Fig. 5: Xperi’s die-to-wafer hybrid bonding flow. Source: Xperi

Die-to-wafer gives packaging customers more options, but it’s a challenging process. “CMOS image sensors are formed with wafer-to-wafer hybrid bonding, where the bonded die have a similar footprint and both wafers have sufficiently high yields with a mature silicon supply chain and process,” said Abul Nuruzzaman, vice president of product marketing at Xperi. “In 2.5D or 3D advance packaging, a die-to-wafer bonding technology is sometimes required. It also requires KGD, different die sizes, and dies from different technology nodes or wafer sizes. Dicing, die handling and assembly must be compatible with the hybrid bonding process, which is relatively new to the industry.”

Besides Xperi, Imec, Intel, Leti, Micron, Samsung, and TSMC are also developing copper hybrid bonding processes.

All copper hybrid bonding processes are similar. First, the desired chip designs are processed on two wafers in a fab. Then, each wafer undergoes a single damascene process in the fab. For this, a dielectric material is deposited on one side of the wafer. On the materials, tiny vias are patterned and etched for each die on the wafer.

Copper materials are then deposited on the wafer. Then, a chemical mechanical polishing (CMP) tool polishes the surface. What remains is copper metallization material in the tiny vias for each die. The exposed copper vias represent the bond pads.

The surface of the wafer must be pristine, with no defects. So after CMP, a metrology tool is used to check the surface topology for defects. Then, the chips are diced on one wafer. Using a wafer bonder, the dies are stacked and bonded onto the second wafer. The final bonded chips are then diced.

It’s a challenging process. During the flow, unwanted particles and defects could surface on the dies. Particles can cause voids in the bond pads. If even a 100nm particle lands on a bond pad, it can result in hundreds of failed connections.

Conclusion
To date, only a few vendors have developed and manufactured chiplet-based designs. Several crucial pieces are falling into place to enable a broader adoption of the technology.

Given the rising costs of developing chips at advanced nodes, the industry needs the chiplet model more than ever.

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Next-Gen 3D Chip/Packaging Race Begins
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What’s Next For Transistors And Chiplets
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3 comments

Riko Radojcic says:

Nice article. As someone who worked on this about a decade ago, my net sense: FINALLY (I am deleting the expletives 🙂

brad jackson says:

Do you have a link to the ODSA Cost Analysis tool?

Mark LaPedus says:

For cost analysis tool, contact ODSA: david@thracesystems.com

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