China Speeds Up Advanced Chip Development


China is accelerating its efforts to advance its domestic semiconductor industry, amid ongoing trade tensions with the West, in hopes of becoming more self-sufficient. The country is still behind in IC technology and is nowhere close to being self-reliant, but it is making noticeable progress. Until recently, China’s domestic chipmakers were stuck with mature foundry processes with no pres... » read more

The Next Advanced Packages


Packaging houses are readying their next-generation advanced IC packages, paving the way toward new and innovative system-level chip designs. These packages include new versions of 2.5D/3D technologies, chiplets, fan-out and even wafer-scale packaging. A given package type may include several variations. For example, vendors are developing new fan-out packages using wafers and panels. One is... » read more

Week In Review: Manufacturing, Test


Chipmakers TSMC has announced its intention to build and operate an advanced semiconductor fab in the U.S. The fab, to be built in Arizona, will utilize TSMC’s 5nm technology and will produce 20,000 wafers per month. TSMC’s total spending on this project will be approximately $12 billion from 2021 to 2029. Construction is planned to start in 2021 with production targeted to begin in 202... » read more

Week In Review: Manufacturing, Test


Fab tools The U.S. Department of Commerce has announced new export control actions to prevent China, Russia, and Venezuela from obtaining U.S. technology for military purposes. This expands the “Military End Use/User Controls (MEU)” license requirement controls on China, Russia, and Venezuela, covering military end-users, as well as semiconductor equipment, sensors and other technologies. ... » read more

3nm: Blurring Lines Between SoCs, PCBs And Packages


Leading-edge chipmakers, foundries and EDA companies are pushing into 3nm and beyond, and they are encountering a long list of challenges that raise questions about whether the entire system needs to be shrunk onto a chip or into a package. For 7nm and 5nm, the problems are well understood. In fact, 5nm appears to be more of an evolution from 7nm than a major shift in direction. But at 3nm, ... » read more

Week In Review: Manufacturing, Test


SPIE At the SPIE Advanced Lithography conference, Lam Research has introduced a new dry resist technology for extreme ultraviolet (EUV) lithography. Dry resist technology is a new approach to deposit and develop EUV resists. It is a dry deposition technique with alternate compositions and mechanisms. By combining Lam’s deposition and etch process expertise with partnerships with ASML a... » read more

Week In Review: Manufacturing, Test


Market research The worldwide semiconductor market is forecast to reach $409 billion in 2019, down 12.8% over 2018, according to the World Semiconductor Trade Statistics (WSTS) organization. Memory fell by 33.0% in 2019, while analog dropped 7.9% and logic declined by 4.3%, according to the WSTS. In 2020, the IC market is expected to recover and grow by 5.9%, according to the WSTS. Optoelec... » read more

Week In Review: Manufacturing, Test


Packaging and test TrendForce has released its top-10 OSAT rankings in terms of sales for the third quarter of 2019. ASE was in first place in the rankings, followed by Amkor and JCET. “According to the latest research from TrendForce, the decline in the global OSAT industry showed signs of a gradual halt in 3Q19, since the drop in memory prices began to slow down, and smartphone sales stead... » read more

Planning For Panel-Level Fan-out


Several companies are developing or ramping up panel-level fan-out packaging as a way to reduce the cost of advanced packaging. Wafer-level fan-out is one of several advanced packaging types where a package can incorporate dies, MEMS and passives in an IC package. This approach has been in production for years, and is produced in a round wafer format in 200mm or 300mm wafer sizes. Fan-out... » read more

What’s The Best Advanced Packaging Option?


As traditional chip designs become more unwieldy and expensive at each node, many IC vendors are exploring or pursuing alternative approaches using advanced packaging. The problem is there are too many advanced packaging options on the table already, and the list continues to grow. Moreover, each option has several tradeoffs and challenges, and all of them are still relatively expensive. ... » read more

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