Old Vs. New Packages


Over the years, the semiconductor industry has witnessed a parade of packaging innovations, such as system-in-package, semiconductor embedded in substrate, and fan-out wafer-level packaging. Two interesting packaging¬†innovations are now being used in the process of miniaturizing microchips and electronics. One is a new concept that combines two tried-and-true technologies. The other is a de... » read more

Bridges Vs. Interposers


The number of technology options continue to grow for advanced packaging, including new and different ways to incorporate so-called silicon bridges in products. For some time, Intel has offered a silicon bridge technology called Embedded Multi-die Interconnect Bridge (EMIB), which makes use of a tiny piece of silicon with routing layers that connects one chip to another in an IC package. In ... » read more

OSAT Consolidation Continues


Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries Ltd. (SPIL) are beginning the process of uniting the two companies, which are among the largest outsourced semiconductor assembly and testing contractors in the world. For now, the companies will continue to operate separately, while their shares are traded under the ASX symbol on the New York Stock Exchange. ASE I... » read more

Packaging Chips For Cars


As the complexity of automotive chips grows, so does the complexity of the package. In fact, packaging is becoming increasingly crucial to the performance and reliability of the chips, and both parts need to meet stringent safety standards before they are used inside a vehicle. This is true for all safety-critical applications, but for automotive in particular there are several key reasons w... » read more

Innovative Integration Solutions For SiP Packages Using Fan-Out Wafer Level eWLB Technology


Fan-Out Wafer Level Packaging (FOWLP) has been established as one of the most versatile packaging technologies in the recent past and already accounts for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduced overall form factor as well as cost effective... » read more

Fan-Out Wars Begin


Several packaging houses are developing the next wave of high-density fan-out packages for premium smartphones, but perhaps a bigger battle is brewing in the lower density fan-out arena. Amkor, ASE, STATS ChipPAC and others sell traditional low-density fan-out packages, although some new and competitive technologies are beginning to appear in the market. Low-density fan-out, or sometimes cal... » read more

Fan-Out Wafer Level eWLB Technology As An Advanced System-In-Package Solution


System-in-Package (SiP) technology continues to be essential for higher integration of functional blocks to meet the ever demanding market needs with respect to smaller form factor, lower cost and time to market. A typical SiP incorporates all or some form of Fan-Out Wafer Level packaging, wire bonding or flip chip that serves a multitude of applications such as optoelectronics, RF, power ampli... » read more

ASE-SPIL Merger Wins Clearance


Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries (SPIL) have finally received all anti-trust approvals for the proposed and long-awaited merger between the two IC packaging houses. The anti-trust approvals are a big step that clears the way for the creation of a combined ASE-SPIL entity. The ASE-SPIL entity, in turn, will create a powerhouse in the outsourced ... » read more

Fine-Pitch Copper Pillar With Bond On Lead (BOL).


Fine pitch copper (Cu) pillar bump adoption has been growing in high-performance and low-cost flip chip packages. Higher input/output (I/O) density and very fine pitch requirements are driving very small feature sizes such as small bump on a narrow pad or bond-on-lead (BOL) interconnection, while higher performance requirements are driving increased current densities. Assembling such packages u... » read more

Board Level Reliability Improvement In eWLB


When it comes to reducing form-factor and increasing functional integration of mobile devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP (FOWLP), it is a more optimal and promising solution compared to fan-in WLP because it can offer greater flexibilit... » read more

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