Managing Thermal-Induced Stress In Chips

Heterogeneous integration and increasing density at advanced nodes are creating some complex and difficult challenges for IC manufacturing and packaging.


At advanced nodes and in the most advanced packages, physics is no one’s friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher density, it makes them more prone to failure due to thermal runaway or accelerated aging.

This becomes even more complicated in heterogeneous designs, where different combinations of materials with varying coefficients of thermal expansion can result in die shift, warpage, and failure to make connections between die. That, in turn, can affect performance and power. Consequently, rather than just relying on the silicon substrate to remove the heat in a planar device at established process nodes, thermal effects need to be identified early, analyzed, and then addressed.

“Co-planarity and warpage are key concerns as we assemble multiple chips — sometimes 7 to 12 on a single organic substrate,” said Ingu Yin Chang, senior vice president at ASE Group. “Localized thermal management is also a concern, because a certain area will have hotspots. That’s something we are working on with our suppliers or customers to identify in the early stages so that we know what to do in terms of overall thermal management.”

These kinds of problems are cropping up everywhere, from PCBs — which are becoming increasingly dense, as well — all the way into the most advanced packages. Consider copper balance, for example, which is a way to symmetrically distribute copper traces in every layer of the PCB stack. Chip Greely, vice president of engineering at Promex, said that balance is necessary to avoid board twisting, bowing, or warpage. While copper balance was defined decades ago at the board level, it now has made its way to the chip level. “Copper balance has turned into a problem at the individual package level, where I’m putting in 7, 10, or 12 different devices, flipping them, or die-attaching them onto a substrate at different temperatures.”

Even well-thought-out designs are subject to thermal stresses during manufacturing, and not always in predictable ways. For example, some materials are used for temporary bonding — basically holding a wafer in place while it is bonded to another wafer or individual die or other components. But much of this is done at high temperatures, and the challenge is to figure out the precise temperature and time that are required for these different steps, and re-engineer the materials used in those steps because the heat can cause mechanical failure and other stresses, including die shift and warpage.

“We’ve had to go ahead and create new programs associated with cleaning-defectivity testing, because what everyone is asking for is materials with really high temperature stabilities — like 400° and higher,” said Kim Yess, executive director of the WLP Business Division at Brewer Science. “And then, once you get it to survive something like that, or to be able to survive harsh chemicals, then it’s going to be even more difficult to get it off in a reasonable manner with fab-safe type materials. This has spawned some other program activities that a few years ago we never anticipated we would need, or need to this extent.”

In heterogeneous packages not every component can withstand the same amount of heat, and that becomes even more complicated as dimensions shrink.

“The manufacturing step is completely dominated by the temperature,” said Herman Oprins, principal member of technical staff, R&D team leader — thermal modeling & characterization at imec. “Your whole assembly will be at some set temperature distribution. You do one processing step and then you go to the next steps, which all have their temperature levels, and then you cool down to room temperature and that creates the thermal contrast.”

This can cause latent defects that may not show up for months or years in the field. “Having no stress at room temperature may not be the best solution because once you start cycling you will power on and off several times,” said Mario Gonzalez, scientific director and R&D Manager for mechanical and thermal modeling and characterization at imec. “When you start cycling, you create fatigue failures that cannot be detected during the processing. Sometimes, we’ve seen the whole PCB bending because of high temperature. Those effects are also difficult to predict because most of the analysis is done at the package level but not during the integration of the whole system. So if you do the inspection at wafer level and you don’t observe anything, it doesn’t mean that a package level or system level it will not fail, because it’s the combination of factors that makes this failure.”

Fig. 1: 3D packaging landscape, with increasingly tight pitches for interconnects and density. Source: imec

There are a number of different approaches to dealing with these problems. One is to alter the chemistry of the materials being used. A second is to reduce the amount of heat being generated. A third is to remove as much heat as possible. Increasingly, all three approaches are required.

“Stress caused by different material CTEs combined with cooling and heating are always present in an IC package,” said Mike Kelly, vice president of Advanced Package & Technology Integration at Amkor. “Good material selections can help, as well as minimizing high temperatures during manufacturing.”

His colleague Nathan Whitchurch, senior staff engineer Amkor, gave some additional advice: “Proper material selection is key, and each package configuration may have its own unique optimum configuration that balances and compromises competing requirements (e.g., flexibility and thermal conductivity). It’s not fair to expect that a certain material set will work well across many package types and sizes.”

In addition, with mechanical stress, the strength of the materials can be increased, effectively adding mechanical margin. “Stress can go in either direction, sometimes it’s tensile, sometimes it’s compressive,” said Oprins. “You can use simulation to try to optimize what are the best combination of materials and their dimensions and densities to minimize the stress.”

Solutions to mechanical stress must be tuned for different applications/scenarios. “Usually, simulation plus measurement validation are needed to provide reasonable optimizations on design, process, material, etc. to enable robust product development,” said a JCET spokesperson. “In terms of TIMs, for high-power devices, low thermal resistance — including interface resistance — is key. And metal TIM (e.g., solder TIM, liquid metal TIM) might be adopted quickly by the industry. For mobile devices — not high power, but strict environment conditions — advanced materials such as graphite might be more popular. Some other factors such as reparability will also play a role in material and process selection.”

And while it’s tempting to see stress as a universal enemy, it also has its place as a strategy. “On the packaging side, you try to reduce stress,” said imec’s Gonzalez. “At the transistor level, if you add compressive stresses, you increase mobility, which makes the transistor work with higher efficiency. That’s why you use trench isolation, or you add some nitrous oxide to increase the stress in silicon or silicon germanium.”

Solder and stress
At the heart of many of the problems at advanced nodes is a staple that goes back to the earliest days of metal-working — solder. Fortunately, it also can provide a solution, acting like a shock absorber.

“Solder can accommodate differences in thermal expansion coefficients,” said Tom Marinis, a principal member of the Laboratory Technical Staff at Draper. “That’s why it’s been useful for flip chip attachment. It can bridge that difference in the inherent thermal expansion coefficients of those materials.”

Solder offers both challenges and solutions at advanced nodes. “The industry roadmap shows a hybrid bonding approach, like Cu-to-Cu direct bonding a pitch under 10um,” according to the JCET spokesperson. “Thermo-compression bonding (TCB) helps to achieve quality solder bonding with some warpage, although compression helps to overcome the intrinsic warpage. TCB with NCP/NCF (non-conductive paste/film) helps to address the challenges of large die/small pitch/capillary underfill or a pre-dispensed underfill. One possible disadvantage is when the pitch is getting finer, the nature of forcing the solder in TCB between the Cu tip and die pad protrudes the solder so that shorting between bumps may happen. This is conspicuously different from LAB (laser-assisted bonding), which results in natural melting solder.”

Nevertheless, solder is still a surprisingly accommodating workhorse. “I’ve worked with solder since the C4 days and it keeps advancing into finer and finer pitches,” said Marinis. “It’s a very forgiving, accommodating type of material. It’s challenging doing direct-bond copper, given issues with cleanliness, parallelism, and so forth. Solder can accommodate them because it’s not as sensitive to those kinds of things. It’s a fairly economical solution to some pretty high-tech problems, so I expect it will continue to advance.”

Those advances are key to increased reliability, as Marinis and a colleague demonstrated at last October’s IMAPS. They presented new guidelines [1] for soldering and sealing large, heterogeneous assemblies at wafer level, which should help improve yield by optimizing seal design.

“We have a lot of applications for high-reliability systems where we have to package the die in in a hermetic environment that would operate over an extended period of time—30 or 40 years,” said Marinis. “And the number of die and I/Os are increasing, so we’re working with die in excess of 1,000 I/Os and putting several of these together in a system. Trying to incorporate them in ceramic packages is becoming more challenging.”

Draper engineers investigated the interplay between seal width, solder volume, and the gap between seal surfaces. They focused on problems such as wafer bow and irregularities in the seal surfaces, and they compared solder that’s applied to flat surfaces and solder that bridges a gap between surfaces. Their models predicted the solder’s behavior in several settings, providing a decision-support tool for microelectronics manufacturers.

“The surface tension of the solder is very strong,” explained Marinis. “What the solder tries to do is minimize its area, like a wire would melt and form a ball. But if it has a surface that wets, that impacts surface energy, so what you’re trying to do is minimize the overall energy. If you want to make a seal between two wafers, you have to account for the energy that’s in the sidewalls, the the free solder, and also the energy of the solder that’s in contact with the two wafers. Adding those energies together, what it attempts to do is minimize that area or that energy. So in a case where the wafers are too far apart from an energy perspective, instead of having a continuous wall of solder between the two wafers, it would de-wet and form a solder coating on the two separate wafers. And then you would have a loss of hermeticity.”

The goal is to come up with some physics-based approach to minimize the area on the wafer devoted to sealing the chips within a module. To improve the yield for the wafer, most of them would be hermetically sealed. But how all of this will play out amid many other factors that are changing remains to be seen.

Despite ongoing research and continual change, fundamentals still apply. “Advanced packaging still benefits from the ‘traditional’ design concepts, such as careful selection of TIM materials, use of heat spreaders and advanced cooling methods even on the die level (e.g. micro-channel cooling),” said Andras Vass-Varnai, portfolio development executive with Siemens EDA. “On the structural side, the reduction of the CTE mismatch among structural layers is still an important design choice.”

And there is certainly cause for optimism. “We have made a lot of progress with tighter manufacturing tolerances and better material and environmental controls that result in very high quality assemblies that maintain—even improve on—reliability patterns that have been seen in previous generations of products,” said Amkor’s Whitchurch

Nevertheless, there’s still a vast world of variables. “The thing that I would be most worried about are the unknown unknowns,” said Synopsys fellow Rob Aitken. “We think this is a problem. Therefore, we margin for it, we design around it, we build test structures, look at them, measure them, calibrate models, and everybody’s happy. But then you go build something, and it’s ‘Uh-oh, that’s interesting. Who thought of that?’”

—Ed Sperling contributed to this report.


  1. Marinis F. and Soucy J., “Design of Wafer Level Solder Seals—A Surface Energy Perspective,” presented at IMAPS 2022.

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