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Technology Advances, Shortages Seen For Wire Bonders


A surge in demand for IC packages is causing long lead times for wire bonders, which are used to assemble three-fourths of the world’s packages. The wire bonder market doubled last year, alongside advanced packaging’s rise. Wirebonding is an older technology that typically flies under the radar. Still, packaging houses have multitudes of these key tools that help assemble many — but no... » read more

Warpage Of Compression Molded SiP Strips


By Eric Ouyang, Yonghyuk Jeong, JaeMyong Kim, JaePil Kim, OhYoung Kwon, and Michael Liu of JCET; and Susan Lin, Jenn An Wang, Anthony Yang, and Eric Yang of CoreTech System (Moldex3D). Abstract System-in-Package (SiP) technology has been used for a wide range of electronic devices, but the warpage behavior of the package can be difficult to control and predict due to complex manufacturing p... » read more

Chip-Last HDFO (High-Density Fan-Out) Interposer-PoP


Interposer Package-on-Package (PoP) technology was developed and has been in very high-volume production over the last several years for high-end mobile application processors (APs). This is due to its advantages of good package design flexibility, controllable package warpage at room temperature (25°C) and high temperature (260°C), reduced assembly manufacturing cycle time and chip-last asse... » read more

Future Challenges For Advanced Packaging


Michael Kelly, vice president of advanced packaging development and integration at Amkor, sat down with Semiconductor Engineering to talk about advanced packaging and the challenges with the technology. What follows are excerpts of that discussion. SE: We’re in the midst of a huge semiconductor demand cycle. What’s driving that? Kelly: If you take a step back, our industry has always ... » read more

Next Steps For Panel-Level Packaging


Tanja Braun, group manager at Fraunhofer Institute for Reliability and Microintegration (IZM), sat down with Semiconductor Engineering to talk about III-V device packaging, chiplets, fan-out and panel-level processing. Fraunhofer IZM recently announced a new phase of its panel-level packaging consortium. What follows are excerpts of that discussion. SE: IC packaging isn’t new, but years a... » read more

Growing Challenges With Wafer Bump Inspection


As advanced packaging goes mainstream, ensuring that wafer bumps are consistent has emerged as a critical concern for foundries and OSATs. John Hoffman, computer vision engineering manager at CyberOptics, talks about the shift toward middle-of-line and how that is affecting inspection and metrology, why there is so much concern over co-planarity and alignment, how variation can add up and creat... » read more

Making Chip Packaging More Reliable


Packaging houses are readying the next wave of IC packages, but these products must prove to be reliable before they are incorporated into systems. These packages involve several advanced technologies, such as 2.5D/3D, chiplets and fan-out, but vendors also are working on new versions of more mature package types, like wirebond and leadframe technologies. As with previous products, packaging... » read more

Investigation and Methods Using Various Release and Thermoplastic Bonding Materials to Reduce Die Shift and Wafer Warpage for eWLB Chip-First Processes


Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-vias (TSVs). One approa... » read more

Material Solutions For FOWLP Die Shift And Wafer Warpage


By Shelly Fowler Today's fan-out wafer-level packaging (FOWLP) processes use organic substrates composed of epoxy mold compound (EMC) created using a thermal compression process. EMC wafers are a cost-effective way to achieve lower-profile packages without using an inorganic substrate to produce chip packages that are thinner and faster without the need for interposers or through-silicon-via... » read more

Solving Fan-Out Wafer-Level Warpage Challenges Using Material Science


Now more than ever we’re finding that semiconductor process engineers are turning to material scientists to help find solutions for their most complex challenges. Currently, they are looking for ways to improve fan-out wafer-level packaging (FOWLP), one of today’s hottest technologies for heterogeneous integration. Often, with these new advanced solutions come challenges that can impact ... » read more

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