Integration Hurdles For Analog And RF In Next-Gen Packages


A rapid increase in wireless connectivity and more sensors, coupled with a shift away from monolithic SoCs toward heterogeneous integration, is driving up the amount of analog/RF content in systems and changing the dynamics within a package. Since the early 2000s, the majority of chips used at the most advanced nodes were systems-on-chip (SoCs). All features had to fit into a single planar S... » read more

Navigating Heat In Advanced Packaging


The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load. Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than ... » read more

Managing Thermal-Induced Stress In Chips


At advanced nodes and in the most advanced packages, physics is no one's friend. Escalating density, smaller features, and thinner dies make it more difficult to dissipate heat, and they increase mechanical stress. On the flip side, thinner dielectrics and tighter spaces make it more difficult to insulate and protect against that heat, and in conjunction with those smaller features and higher d... » read more

The Path To Known Good Interconnects


Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more