Navigating Heat In Advanced Packaging

New approaches and materials being explored as chip industry pushes into heterogeneous integration.


The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load.

Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than just shrinking digital circuitry to cram more functionality onto a reticle-sized SoC. That raises issues about how to optimize performance and power. On a single die, signal paths can be as short as needed, and the substrate is effective at dissipating the heat. But with multiple dies in a package, substrates and dielectrics need to be thinner to reduce the distance that signals need to travel, and that limits the thermal dissipation.

This can lead to hotspots, which can be hard to predict, particularly under varying workloads and use cases. And it can be made worse when integrating multiple chips or chiplets with varying thermal properties into a single package.

“Anytime you put multiple die on a substrate or interposer, it’s challenging,” says Vik Chaudhry, senior director, product marketing and business development at Amkor Technology. “We are seeing vendors putting not just 3 or 4, but 8 or 10 or 12 die. How do you distribute that heat all around?”

Fig. 1: Simulating heat dissipation at thermal couples. Source: Ansys
Fig. 1: Simulating heat dissipation at thermal couples. Source: Ansys

Heterogeneous integration hinges on the ability to effectively remove the heat, ensuring that the densely packed dies within a module maintain acceptable temperatures for reliable operation. IEEE’s Heterogeneous Integration Roadmap identifies several areas of developmental need, including advanced modeling techniques to predict and manage heat flow, new materials with both high thermal conductivity and low electrical conductivity, and novel cooling solutions that can be seamlessly integrated into complex packages.

Thermal mismatch
Material choices are critical to thermal management in heterogeneous integration. As components with different coefficients of thermal expansion (CTE) heat up and cool down, these materials expand and contract at different rates. That can cause mechanical stresses that compromise the integrity of the chips, weaken the bonds that connect them to interposers or other substrates, and affect the overall functionality of a device.

Employing materials with similar CTEs helps reduce these stresses, mitigating some of the risk of premature failure, as well as other thermally induced effects, such as accelerated aging, reduced electron mobility, or drift in analog or optical signals.

“CTE is probably the number one challenge for advanced packaging, and I don’t think anyone’s really figured it out fully,” says David Fromm, COO and vice president of engineering at Promex Industries. “We’re dealing with CTE on a three-dimensional scale in ways that we’ve never seen before, and these issues with parts warping or breaking are really challenging. Some companies might figure it out for a given process, and then the materials change, the device sizes change, and the equation changes. And then you have to figure it out again.”

Put simply, heterogeneous integration requires a fundamental understanding of the thermal expansion properties of every material that could ultimately shape the reliability and yield of the packaged device. And that’s only part of the problem. Advanced packaging requires an understanding of what else is in the neighborhood of a chip or chiplet, how those other elements are being used, and all of that needs to be modeled and simulated together using what is expected to be a realistic workload. This problem is made much more difficult when compute needs change, such as in data centers where generative AI has significantly increased the amount of data that needs to be processed, resulting in higher utilization of processors and memories.

“There’s always been some level of thermal analysis, but it was done at the end just to check that nothing got too far out of hand,” says Marc Swinnen, director of product marketing at Ansys. “You could target a certain junction temperature, and if it was compliant, it was that simple. But now with multi-die systems, you’re going to have to do that at the RTL floor-planning stage. You’re going to have to have some idea of what the power output of each of these chips is so that two chips that get hot at the same mode of operation aren’t placed right next to each other or right on top of each other. That will doom your design.”

Back to the drawing board
As the industry grapples with various challenges to the heterogeneous integration roadmap, thermal management is no longer an afterthought. It has shifted left in the design-through-manufacturing flow, and out into the field where in-circuit monitors can assess and adjust everything from partitioning to prioritization of different chips and chiplets.

“The devil is in the details,” says Fromm. “These seemingly minor design and integration decisions can have a tremendous impact on whether you can even build what you want, much less build it with yield and product reliability downstream. Choosing the right materials, thinking about the stack ups, and thinking about the process flow are all critical.”

This represents a fundamental shift in an increasing number of designs, from data centers to consumer electronics and increasingly autonomous vehicles. As heterogeneous elements are packaged together in fan-outs with pillars, 2.5D, and especially in 3D-IC designs, thermal paths need to be mapped out in increasing detail. Done wrong, this can cause damage to an entire package filled with multiple chips/chiplets, where even finding the source of the problem can be costly.

“There is a need to design for thermal mechanical constraints as well as the substrate and assembly technology,” says George Orji, research scientist for the CHIPS National Advanced Packaging Manufacturing Program (NAPMP). “Advanced packaging does not allow for rework, so monolithic chip design methodologies for advanced packaging is something that we need to do.”

The complexity inherent in heterogeneously integrated systems demands a multi-disciplinary approach to design. This is complicated stuff, and attempts at making this approach work are not new, and it failed in the face of planar scaling. David Fried, corporate vice president at Lam Research, said during a recent panel discussion that IBM tried 3D heterogeneous integration 25 years ago when he was there. “We thought we could piece together a lot of the process components in it,” he said. “But some of the biggest challenges were on the design and EDA side, partitioning out what technology to use, how to segment the different components of the system on different chips, and then to go back and re-integrate them. The design, and the optimization of the design, has to be there for this to work.”

What’s changed since then is the chip industry has run out of options. It’s becoming too expensive to develop chips at the most advanced nodes, and too constrained by the size of the reticle. But this is still difficult work.

To alleviate the burden on designers, synergistic techniques involving advanced material sciences and computer-aided design tools are increasingly crucial, especially as chip configurations become more intricate and integrated functionality rises. “This is where we still have work to do,” adds Ansys’ Swinnen. “How do we resolve this in a way that doesn’t require every designer to be an expert in thermal and an expert in electromagnetic interference and an expert in mechanical? It’s unrealistic to expect that of our design community.”

With these constraints comes the necessity for innovation in several key aspects of the design process. Recognizing the multi-faceted nature of heat generation within densely integrated chips, it is imperative to address not just steady-state, but also transient thermal events, which are largely based on use-cases or workloads. The roadmap for heterogeneous integration includes strategies like 3D thermal interface materials and CTE-matched heat spreaders to ensure even heat distribution.

“With multiple dies, you have multiple sources of thermal effects, multiple mechanical gradients and temperature gradients,” says Manuel Mota, senior product marketing manager at Synopsys. “All of this must be addressed in the design phase.”

Integrating thermal considerations into the design process is a requirement for the practical realization of any complex semiconductor device. It’s not just about identifying the right materials or components. It’s also envisioning how they will all function collectively in the field.

As engineers reduce the form factor of electronic devices while ramping up their performance, the thermal envelope tightens significantly. Comprehensive management of thermal profiles across different operational states, leveraging the latest heat spreader and thermal interface materials, becomes essential to maintain device integrity and performance over its intended lifecycle.

“Thermal is the number one limitation for integration density,” says Swinnen. “It’s easy to stack the chips. You can manufacture it and you can design it, but it will never work because it will get too hot. So thermal has become a central part of every 3D-IC chip designer’s concern.”

Resolving the thermal challenge in heterogeneous integration requires putting together different materials, such as semiconductors with lower CTEs, like silicon, with metals like copper or aluminum, to effectively dissipate heat. Unfortunately, this mix of materials often leads to warping, cracks, solder bump lifting, and devices failing earlier than expected. New materials are needed that have compatible properties to overcome these issues.

“These substrate materials will probably develop more slowly than the interface materials, adhesives, epoxies, and so forth,” says Fromm. “It comes down to process conditions and how you manage those. Where we can be better on the processing side is working with the adhesive manufacturers to understand changes in temperature, and then upstream at the design level to understand how all of these stacks can evolve, considering those changes in temperature.”

Material innovations
Thermal concerns extend well beyond just the chip’s operation. Heat is an issue on the manufacturing side, as well. The chips inside an advanced package have to survive assembly and manufacturing, where some of the same CTE issues can become problematic.

Consider collective die-to-wafer (CoD2W), for example, which uses thermo-compression bonding to attach a die to a wafer. “In the CoD2W process, there are situations where different die come from different sources, and can have different heights or different thicknesses,” says Rama Puligadda, executive director of advanced technologies R&D at Brewer Science. “When you populate a carrier with these dies, it’s very difficult to know if all the dies will make contact with the target during bonding. The mechanical properties of the die-attach adhesive are designed to allow the taller die to get slightly embedded during bonding, which enables good contact of all dies to the target wafer.”

That raises different issues. “Challenges for our materials include temperature limitations of different die,” Puligadda said. “We have to ensure that the temperatures used for bonding materials don’t exceed the thermal limitations of any of the chips that are being integrated into the package. Additionally, there may be some subsequent processes like redistribution layer formation or molding. Our materials have to survive those processes. They have to survive the chemicals they come in contact with throughout the packaging process scheme. Mechanical stresses in the package add additional challenges for bonding materials.”

A range of materials is in development that offers superior thermal conductivity as well as electrical insulation. These newly engineered thermal interface materials (TIMs) provide efficient heat conduction pathways between a chip and its cooler without interfering in the chip’s performance. TIMs not only boast improved thermal conductivity but also cater to the minute variances induced by uneven heat generation across the chip’s surface.

“Thermal management will require new thermal materials, as well as novel circuit topologies that employ advanced substrates and heterogeneous integration,” says Orji. “Because the chips are packed so close to each other, there’s very limited ability to spread excess heat.”

Fig 2: Detailed view of a particle-laden polymer thermal interface material. Source: Amkor
Fig 2: Detailed view of a particle-laden polymer thermal interface material. Source: Amkor

Ideally, these new materials will exhibit strong covalent bonds and balanced anion-cation masses, akin to the uncomplicated atomic structure found in diamond. Recognized materials in this category include diamond, along with compounds like beryllium oxide, aluminum nitride, boron nitride, and, to some extent, silicon nitride. Despite their thermal conduction capabilities, these materials pose manufacturing challenges due to the very bonds that provide their strength, necessitating high-temperature sintering processes, for instance, to achieve the desired density. An exception is diamond, which does not lend itself to sintering.

One approach to harnessing the benefits of these materials, despite their processing challenges, includes utilizing composites. For example, incorporating aluminum nitride within an epoxy composite partially captures the thermal handling advantages, although it won’t match the conductivity levels of a solid ceramic counterpart. This blend of material properties is crucial in electronics packaging, where it’s desirable to have an excellent electrical conductor that draws enough heat away from the chip cores to prevent compromises in signal performance.

Diamond, celebrated for its extreme hardness, stands out as an exemplary thermal conductor and insulator. Polymeric materials like Teflon (Polytetrafluoroethylene, or PTFE), though less conductive than ceramics or diamond, still surpass many plastics in their ability to conduct heat and offer reliable electrical insulation. PTFE is effective enough to be employed as coating materials in heat-intensive applications such as cookware.

Glass, porcelain, and other dense ceramics share these insulating and heat conduction properties. They make for practical solutions, particularly in cases where an excellent electrical insulator is also required to manage heat. Aluminum nitride (AlN) is utilized as an insulator in semiconductor devices, bridging the gap between dies and heat transfer components. Despite not being as thermally conductive as beryllium oxide, AlN offers a safer and more cost-effective alternative. Additionally, AlN surpasses more standard insulators like mica, polyimide, and alumina regarding thermal management.

Synthetic sapphire also merits attention due to its affordability and malleability into various forms, making it another valuable player in the semiconductor packaging space. Each of these materials presents unique advantages in the design of packages where controlling heat without hampering electronic performance is paramount.

While advanced materials like diamond and aluminum nitride are at the forefront of tackling thermal challenges in semiconductor devices, not all solutions require exotic or rigid components. Thermal greases and adhesives serve as the connective tissue in electronic packaging, filling small gaps or surface irregularities and facilitating heat transfer between components with varying topographies. Their ability to conform to surfaces provides a crucial complement to the more solid thermal management solutions, forming a comprehensive approach to heat dissipation. With a focus on improving these materials, researchers aim to enhance their thermal conductivity properties, making them more effective partners in the heat management paradigm.

“Thermal greases and thermal adhesives are thermally conductive,” adds Fromm, “But compared to materials like a typical ceramic that are thermally conductive, they’re terrible conductors by a factor of ten. These materials aren’t that good, and there are physical and chemical reasons why. There’s a lot of upside to be achieved there, and there’s a lot of work happening in that space.”

Looking ahead
As new materials pave the way for thermal relief, innovative new cooling techniques are also in development. Silicon micro-channels, which are micro-scale pathways etched into substrates, can route coolants directly to the heart of hotspots. This direct cooling method is superior to traditional heatsinks but offers challenges in design, assembly, and reliability.

Similarly, the development of closed-loop liquid cooling systems could allow components to stay cool without the constraints imposed by air flow methods. These systems offer the promise of a cooler operational temperature without the threat of thermal throttling, but there is much research to be done in both design and process handling for liquid cooling systems.

Another option is to simply reverse the structure of stacked die, so instead of putting memory on top of logic, the logic is put on top of memory with a heat sink on top. Winbond, for one, suggested this with its customized ultra-bandwidth elements (CUBE) technology, a high-performance approach that stacks the SoC top die directly to the memory, which is then attached to the substrate using through-silicon vias. The approach, according to C.S. Lin, marketing executive at Winbond, uses less power, which in turn reduces the heat. In addition, it allows the heat to be removed directly, rather than channeling it through some labyrinth of heterogeneous components.

Another option is to use real-time thermal management, powered by AI. Algorithms now can monitor temperatures across various on-chip locations, directing cooling resources dynamically, ensuring optimum performance without crossing the thermal red line. ProteanTecs, for example, just rolled out a solution aimed at the data center that it says can lower the power in servers by reducing the amount guard-banding needed to protect the chips from overheating. This approach relies on monitoring changes from within a chip and providing adjustments as needed.

Synopsys and Siemens EDA also have solutions in place to monitor different activity and temperature changes using internal sensors. Being able to get readouts from inside a package using telemetry is an increasingly important component in managing heat.

“You have the mechanical construction of chips on chips and on interposers with thousands or millions of micro-bumps, and they all expand and contract as the chip warms up,” adds Swinnen. “Depending on your thermal map, your power integrity will have to adapt to the local temperature profile in real time. You can calculate how much power a chip is putting out, but what temperature that brings it to depends. Is it sitting on a cold plate, or is it sitting in the sun in the Sahara? The same chip and the same activity can lead to very different temperatures depending on its surroundings.”

Additionally, research into phase-change materials, which absorb heat by changing their state, promises passive yet potent temperature regulation. More so, the exploration into biological cooling systems, trying to mimic the human body’s response to heat, portends a future where our devices can dissipate heat as intuitively as we perspire.

As the semiconductor industry continues to push the boundaries of performance and integration, the thermal management within advanced packaging remains a challenge. On one side of the spectrum, escalating thermal complexities emerge as companies drive towards more densely packed multi-chip modules. On the opposite, advancements in material sciences and innovative cooling technologies strive to alleviate the resultant thermal strain. Both are required to address complex thermal challenges, but there is a lot of work still ahead to solve this in a consistent and predictable way.

— Ed Sperling contributed to this report.

Related Reading
Managing Thermal-Induced Stress In Chips
Heterogeneous integration and increasing density at advanced nodes are creating some complex and difficult challenges for IC manufacturing and packaging.

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