Reducing Advanced Packaging Costs


Semiconductor Engineering sat down with Chenglin Liu, director of package engineering at Marvell; John Hunt, senior director of engineering at ASE; Eric Tosaya, senior director of package manufacturing at eSilicon; and Juan Rey, vice president of engineering for Calibre at Mentor, a Siemens Business. What follows are excerpts of that discussion, which was held in front of a live audience at MEP... » read more

What’s the Right Path For Scaling?


The growing challenges of traditional chip scaling at advanced nodes are prompting the industry to take a harder look at different options for future devices. Scaling is still on the list, with the industry laying plans for 5nm and beyond. But less conventional approaches are becoming more viable and gaining traction, as well, including advanced packaging and in-memory computing. Some option... » read more

Why Test Costs Will Increase


The economics of test are under siege. Long seen as a necessary but rather mundane step in ensuring chip quality, or a way of testing circuitry from the inside while it is still in use, manufacturers and design teams have paid little attention to this part of the design-through-manufacturing flow. But problems have been building for some time in three separate areas, and they could have a b... » read more

Defect Challenges Growing In Advanced Packaging


The current defect inspection systems for packaging are running out of steam for the latest advanced packages, prompting the need for new tools in the market. In response, several vendors are rolling out new defect inspection systems for use in various advanced packages, such as 2.5D/3D technologies and fan-out. The new defect inspection systems are more capable than the previous tools, but ... » read more

Old Vs. New Packages


Over the years, the semiconductor industry has witnessed a parade of packaging innovations, such as system-in-package, semiconductor embedded in substrate, and fan-out wafer-level packaging. Two interesting packaging innovations are now being used in the process of miniaturizing microchips and electronics. One is a new concept that combines two tried-and-true technologies. The other is a de... » read more

Scaling Sideways


The next steps in semiconductor technology don't follow the same vectors. While 3nm chips are likely to roll out at some point in the future, it's not clear what the business case will be for developing them. What's clear is the number of companies developing chips at that node will shrink to a handful (or less), because they're going to be far too expensive to design, verify and manufacture... » read more

7nm Design Challenges


Ty Garibay, CTO at ArterisIP, talks about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm. https://youtu.be/ZqCAbH678GE » read more

Advanced Packaging Confusion


Advanced packaging is exploding in all directions. There are more chipmakers utilizing different packaging options, more options for the packages themselves, and a confusing array of descriptions and names being used for all of these. Several years ago, there were basically two options on the table, 3D-ICs and 2.5D. But as chipmakers began understanding the difficulty, cost and reduced benef... » read more

OSAT Consolidation Continues


Advanced Semiconductor Engineering (ASE) and Siliconware Precision Industries Ltd. (SPIL) are beginning the process of uniting the two companies, which are among the largest outsourced semiconductor assembly and testing contractors in the world. For now, the companies will continue to operate separately, while their shares are traded under the ASX symbol on the New York Stock Exchange. ASE I... » read more

The Case For Chiplets


Discussion about chiplets is growing as the cost of developing chips at 10/7nm and beyond passes well beyond the capabilities of many chipmakers. Estimates for developing 5nm chips (the equivalent 3nm for TSMC and Samsung) are well into the hundreds of millions of dollars just for the NRE costs alone. Masks costs will be in the double-digit millions of dollars even with EUV. And that's assum... » read more

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