New Interconnect Materials Beyond Copper (Florida State Univ., Cornell)


A new technical paper titled "Shrinking interconnects beyond copper" was published by researchers at Florida State University and Cornell University. Excerpt "The continuous downscaling of transistors in integrated circuits following Moore’s law—doubling the number of transistors on a microchip about every 2 years—has been an extraordinary feat of engineering, pushing the limits of fu... » read more

Framework for Optimizing Reliability and Thermal Management of 3DICs (National Taiwan Univ., Lamar Univ.)


A new technical paper titled "The Impact of Process Variations on the Thermo-Mechanical Behavior of 3D Integrated Circuits" was published by researchers at National Taiwan University and Lamar University. Abstract "The use of vertically stacked architectures in three-dimensional integrated circuits (3DICs) offers a transformative path for advancing Moore’s Law by significantly boosting co... » read more

Transformational Opportunities Coming To Semiconductor Manufacturing


During the GSA US Executive Forum in September 2024, a panel discussion brought together Marco Chisari, EVP from Samsung Semiconductor, Jeff Howell, Global VP for High Tech at SAP, and John Kibarian, CEO of PDF Solutions. The purpose of the discussion was to compare and contrast the perspectives from one of the largest global semiconductor companies with that of the most widely used enterpri... » read more

Navigating Heat In Advanced Packaging


The integration of multiple heterogeneous dies in a package is pivotal for extending Moore’s Law and enhancing performance, power efficiency, and functionality, but it also is raising significant issues over how to manage the thermal load. Advanced packaging provides a way to pack more features and functions into a device, increasingly by stacking various components vertically rather than ... » read more

Energy Usage in Layers Of Computing (SLAC)


A technical paper titled “Energy Estimates Across Layers of Computing: From Devices to Large-Scale Applications in Machine Learning for Natural Language Processing, Scientific Computing, and Cryptocurrency Mining” was published by researchers at SLAC National Laboratory and Stanford University. Abstract: "Estimates of energy usage in layers of computing from devices to algorithms have bee... » read more

Sweeping Changes For Leading-Edge Chip Architectures


Chipmakers are utilizing both evolutionary and revolutionary technologies to achieve orders of magnitude improvements in performance at the same or lower power, signaling a fundamental shift from manufacturing-driven designs to those driven by semiconductor architects. In the past, most chips contained one or two leading-edge technologies, mostly to keep pace with the expected improvements i... » read more

Challenges In Ramping New Manufacturing Processes


Despite a slowdown for Moore’s Law, there are more new manufacturing processes rolling out faster than ever before. The challenge now is to decrease time to yield, which involves everything from TCAD and design technology co-optimization, to refinement of power, performance, area/cost, and process control and analytics. Srinivas Raghvendra, vice president of engineering at Synopsys, talks abo... » read more

Preparing For Commercial Chiplets


Experts at the Table: Semiconductor Engineering sat down to discuss the path to commercialization of chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts of tha... » read more

Specialization Vs. Generalization In Processors


Academia has been looking at specialization for many years, but solutions were rejected because general-purpose solutions were advancing fast enough to keep up with most application requirements. That is no longer the case. The introduction and support of the RISC-V processor architecture has attracted a lot of attention, but whether that is the right direction for the majority of modern comput... » read more

RISC-V Driving New Verification Concepts


Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

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