Preparing For Commercial Chiplets

Experts at the Table: Semiconductor Engineering sat down to discuss the path to commercialization of chiplets with Saif Alam, vice president of engineering at Movellus; Tony Mastroianni, advanced packaging solutions director at Siemens Digital Industries Software; Mark Kuemerle, vice president of technology at Marvell; and Craig Bishop, CTO at Deca Technologies. What follows are excerpts of that discussion, which was held in front of a live audience at the recent Design Automation Conference. View part two of this discussion. Part three is here.

[L-R] Ed Sperling, Semiconductor Engineering; Mark Kuemerle, Marvell; Craig Bishop, Deca Technologies; Tony Mastroianni, Siemens EDA; Saif Alam, Movellus.

SE: There’s been a lot of discussion and debate about chiplets. Why do we need them?

Kuemerle: One of the one of the reasons we use chiplets is, quite frankly, because we have no other alternatives. Semiconductor scaling is slowing down. Chips are getting bigger and bigger to get the performance increase people need from generation to generation. So you need a way to get more silicon into a system that you’re building, and one way to do that through chiplets.

Bishop: Another thing we’re seeing — and it’s already out there in high volume with AMD’s RDNA 3 product — is chiplets developed at two different nodes in the same package At the same time, they use a novel form of packaging technology to put chiplets together. It wasn’t a silicon interposer. It’s fan-out-based chiplet integration. So you have the need to put more chiplets together, and there are more options than ever before for advanced packaging technologies.

Mastroianni: I agree that one of the key advantages is you can use different technologies. So for different parts of your system, you can optimize the technology or the process. For example, for the I/O buffer, you can use high-performance RF. You can mix and match the technology that best suits your needs.

Alam: Until around 2006, you would improve chips and productivity just by upgrading to the latest process. But then what happened is the cost didn’t scale with transistors to the next process node, so it became more and more expensive to go to smaller technology. And when you move to very large chips, you can’t even fit everything into the size of the reticle, so you have no option other than going to chiplets. There are other benefits, though, like improved yield because those are smaller die, and lower NRE costs.

Mastroianni: Another benefit is form factor. Depending upon your application, if you go 3D, you have a lot more flexibility in terms of how large that system is.

SE: The yield for individual chips is generally higher when you reduce the size. But now we’re dealing with yield in a package, so every chiplet needs equivalent yield. Is this simpler than with a single, large SoC?

Bishop: We get that question a lot. We work on advanced packaging technology, and a lot of people looking at chiplets — especially on the AI side, because AI is hungry for as much chip area and as much memory as you can throw at it — the package starts to get huge. We’re talking 70 to 100 millimeters, not just for substrate size, but actually full of silicon. And when you look at how you put that together, it’s not going on a traditional silicon interposer, because it’s too big. It’s using one of these other advanced packaging technologies, like a fan-out bridged die. And now we’re talking about building a wafer-level package with multiple metal layers, that’s so big only four or five of them fit on a single 300 millimeter wafer. Even the 600 millimeter technology we work on only fits a few of those at every quadrant. And you’re building probably hundreds of thousands of fine vias for every for every metal layer, and putting that into a packaging technology that’s only been around for the last 10 years. Traditionally, they’ve been making parts for smartphones that are maybe 3 by 4 millimeters. This is not the same wheelhouse. We’re going far beyond that, and yield is a huge challenge. I can optimize all I want on the front-end node when I buy my chiplet, but if my package doesn’t yield I still have a problem.

Kuemerle: One of the phenomena we see is that it doesn’t always help to build things as chiplets. If you break things into smaller pieces, that helps the yield quite a bit. But if you’re talking about 2.5D integration with a traditional silicon interposer, you’re adding costs. In some cases, you’re adding more cost than you’re saving by partitioning designs into smaller pieces. As an industry, we need to figure out what the right balance is. When do you make something as a chiplet? When do you leave it alone as monolithic? And are there in-between technologies where you can have the benefit of integrating as a chiplet without the huge added cost of integration with 2.5D.

Bishop: It’s not just added cost. It’s also fewer options. If you look at advanced packaging, the number of companies that can assemble it for you and manufacture it shrinks very quickly.

Mastroianni: The reason for doing it can vary by product. It may be a different answer if you’re worried about cost, area, or form factor. It depends on what you’re trying to build, what are the objectives of that product, and how you’re going to partition that into chiplets if you decide to do that.

Alam: You’re testing the chiplets by themselves, and testing at every level. But whenever it fails, you lose all of that.

SE: This sounds very similar to the discussions we used to have about subsystems years ago. Now, instead of a subsystem with different chips, you have an advanced package with different chiplets.

Bishop: An HBM stack, which is a very popular chiplet, is a great example of that. It’s probably the most successful chiplet in the market today. When you buy an HBM stack, it’s assembled on multiple pieces of silicon and it’s fully tested for you. And when you integrate that HBM, you expect it to work.

Kuemerle: And one thing that really helps is a very rigorous and defined interface, and a very rigorous and defined functionality. It’s something we’re not seeing across the market. How do you enforce that kind of absolutely hard criteria, like the JEDEC spec for HBM, for broader applications in chiplets? So far what we’re seeing in the industry for I/O chiplets and other things like that tend to be bespoke solutions. How do we, as an industry, move toward having the same kind of plug and play?

Alam: It probably won’t be just be one standard. There are advantages for different interface protocols. It probably will be multi-faceted.

Bishop: Absolutely. People say chiplets will be like PCBs, where you can get components from different places and put them on the same package. But when you look at PCB communication standards, there’s a whole bunch of standards, not just one to rule them all. So we’ll be in the same boat.

SE: Do the tools exist today to be able to pull this all together?

Mastroianni: Yes, with the exception of 3D packaging, which is still a work in progress. The challenge is there are packaging tools, thermal tools, and IC tools, and the challenge is really getting the tools to work together. That requires a lot of work. Defining standards is important. Data management is a big issue. Tools do exist, but they have to work together.

Bishop: It’s not just getting the tools to work together. It’s also the teams and the people. The package team and the IC team know what extraction means, but that hasn’t always been common.

Mastroianni: When we simulate chips, the IC team is talking about functional simulators. The packaging team is talking about extracting a parasitic. So you need a common language, too.

Alam: For chiplet design you need a platform-level view. You need one level that goes for the entire platform for functional validation.

Mastroianni: I call that the system-in-package level, and there are tools out there to help with that. And then we have DRC and LVS checkers to help.

SE: The chiplets we’ve seen so far have come out of large companies, like Marvell, Intel, and AMD. What’s going to happen when we get into a commercial marketplace?

Kuemerle: Building a chiplet-based system is not easy. There are a lot of things you have to consider. It requires drastic changes to your packaging solution, and it changes your verification considerably. So there are a lot of problems you need to solve for, and what we’re seeing now is people are solving those mostly in-house, or they’re ordering a bespoke chiplet themselves from another party because it gives you a degree of control. As an industry, we have to figure out how do we get to a point where we can trust each other with very critical and sensitive data so that we can open up interoperability with more chiplets. Maybe a strategy is rigid enforcement like HBM. Or maybe another strategy is figuring out what’s really critical IP that needs to be protected. Right now we don’t have an easy way to share chiplets with people who could be fierce competitors.

Mastroianni: There’s an organization called the Chiplet Design Exchange (CDX), which is a working group in OCP (Open Compute Project). The charter of that group is an open ecosystem. You have a methodology, standard interfaces, and standards. The first thing we took a look at is, if we have a vendor providing chiplets, what did they deliver? It’s really a piece of IP that’s analogous to silicon IP, but in this case it’s a chiplet that’s going to be integrated into a package. The models that get delivered with that need to be defined. We’ve defined it as a list of recommendations. When you’re delivering something to be integrated into a package you need a thermal models and other models — you need a whole collection of these. And you also need the test patterns for what gets tested.

Bishop: You need the design tools, and you need a way to exchange chiplet information, but you also need the availability of the technology to put them together. For more than a decade, that’s been a silicon interposer. Or, you can put chips on a substrate together. But we’re pushing the definition of chiplet. When people talk about chiplets at conferences now, we’re talking about very fine pitch integration, where it’s almost like one piece of silicon into another piece of silicon. Until recently, no other companies besides the big companies have been able to access that type of integration technology. We’re trying to spread that capability so more companies can do that. But even today, when you offer a chiplet, you’re very much tying your customers into a certain type of integration — often at a certain company on a certain platform. And that’s still a challenge if you’re trying to sell a generalized, usable chiplet that you want customers to use on all kinds of devices. That’s still very tough today.

Kuemerle: There’s a lot of work going on in the industry today around interoperable interfaces, and there’s work underway to determine whether we have interoperable link layers. But the one thing we’re missing is the ability to think about chiplets like a LEGO set. If you buy a LEGO set, everything goes together and there are instructions. A kid can put it together and build something that looks like it’s supposed to look. With chiplets, you’re breaking a lot of packaging rules by putting lots of disparate shapes together. We still have to figure out how to make that work.

Mastroianni: A place to start is defining a set of formats where we have the same language to define these rules. Once you have that, then we can decide on a common set of rules for the assemblers — the OSATs. The different chiplet vendors have to come up with a common set of rules. The first thing is formats so we can have the same language, and then collaboration.

Alam: You do need a common platform where you can invoke these rules. But that doesn’t mean there’s only one way to do it.

Mastroianni: A lot of the design kits in the chip world are delivered as very rigid standards, and everyone knows what a PDK is. In the packaging world, not so much. You’re getting that information from PDFs. So if we can define formats to have that information in a machine readable format, then we have the same language. Whatever tools you’re using are just reading that format. The rules still have to be decided, but at least if we build our tools and workflows that can read that format, we can build that into our scripts.

Bishop: That actually may be a call to action we can take. We need to push OSATs to adopt industry standards, because traditionally it has not been there in packaging. It’s been there for decades with PDKs at the front end, but in packaging it’s been a PDF. And until customers don’t accept that and say, ‘Hey, I don’t want your PDF, I want your design kit with the rules specified formally.’ Until you stop accepting that PDF, it’s going to continue.

Mastroianni: We initiated an effort for 3D design kits. It’s a collection of models for everything that’s been assembled from a design kit. We have a working group with foundries and OSATs and users —the people who are doing designs — and we have chiplet providers. We’re working together with multiple EDA vendors. So rather than pushing our individual formats, we’ll have
a common format. That’s going to help a lot with end users because they will have common data.

View part two of this discussion: Why Chiplets Don’t Work For All Designs.

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Chiplets: Deep Dive Into Designing, Manufacturing, And Testing
EBook: Chiplets may be the semiconductor industry’s hardest challenge yet, but they are the best path forward.