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3D ICs

2.5D and 3D forms of integration
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Description

Two or more integrated circuit dies that are stacked on top of each other. The access mechanism connects only to the bottom die.

Fig. 1: Vidya Neerkundar, technical marketing engineer at Siemens EDA, explains 3D-IC with a sketch she drew of a basic 3D-IC. Watch this video for more explanation.

The classic definition that has emerged for 3D ICs is logic on logic, connected with through-silicon vias (TSV). But there are other iterations of this idea, ranging from package-on-package (PoP), homogeneous memory stacks on logic, and hybrid chips that combine some elements of 2.5D with 3D memory and almost-3D memory. There are even some new approaches being presented, including wireless connectivity between very thin die, and wafer-level packaging rather than die-on-die packaging.

 

 


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