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3D ICs

2.5D and 3D forms of integration
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Description

Two or more integrated circuit dies that are stacked on top of each other. The access mechanism connects only to the bottom die.

The classic definition that has emerged for 3D ICs is logic on logic, connected with through-silicon vias (TSV). But there are other iterations of this idea, ranging from package-on-package (PoP), homogeneous memory stacks on logic, and hybrid chips that combine some elements of 2.5D with 3D memory and almost-3D memory. There are even some new approaches being presented, including wireless connectivity between very thin die, and wafer-level packaging rather than die-on-die packaging.

The main issue with 3D-ICs is thermal. Chips generate heat and when they are stacked on each other, that heat needs to go somewhere without damaging the chips. The chips also need a power — thermal and power are interrelated. Thermal is a direct result of power, which is a result of activity. The thermal energy released in the circuit is very dependent on the short- and long-term activity profiles. With 3D-ICs, chiplets of varying sizes and types (memory, logic, mixed-signal) are put together in a package, so it is more complex to design and test. That’s made worse by the fact that the target market, at least today, is generative AI in data centers. “Especially when we’re looking at the data center infrastructure space, the power consumed by these processes is humongous,” said Sudhir Mallya, senior vice president of corporate marketing at Alphawave Semi. “Stacking the processor with other chiplets is a technology problem that has not been solved. That’s why we’re still seeing a lot of 2.5D. With a high-bandwidth memory (HBM) stack, all the memories are identical in size, and the power is identical. So from a thermal management and reliability point of view, that’s much easier to solve compared to 3D-ICs, where you have different sizes of chiplets and different power coefficients.”

 


Fig. 1: 3D-IC concept. Source: Siemens EDA

Fig. 1: Vidya Neerkundar, technical marketing engineer at Siemens EDA, explains 3D-IC with a sketch she drew of a basic 3D-IC. Watch this video for more explanation.


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