Knowledge Center
Knowledge Center

Physical Verification

Making sure a design layout works as intended.


Physical verification is the process of ensuring a design’s layout works as intended. Steps include design rule checking (DRC) and layout-versus-schematic (LVS) checks.

Design rule checking (DRC) determines if a chip layout satisfies a number of rules as defined by the semiconductor manufacturer. Each semiconductor process will have its own set of rules and ensure sufficient margins such that normal variability in the manufacturing process will not result in chip failure.

Layout vs. schematic (LVS) provides device and connectivity comparisons between the IC layout and the schematic. An LVS tool enables accurate circuit verification because it is able to measure actual device geometries across a full-chip for a complete accounting of physical parameters. The measured device parameters supply the information for back-annotation to the source schematic and comprehensive data for running simulations.