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IEEE 1076.4-VHDL Synthesis Package – Floating Point

Modeling of macro-cells in VHDL


The goal of VITAL (VHDL Initiative Towards ASIC Libraries) was to accelerate the development of sign-off quality ASIC macro-cell simulation libraries written in VHDL by leveraging existing methodologies for model development. In addition due to the slowness of VHDL gate-level simulation, the 1076.4 working group provided a mechanism to allow faster gate-level simulation using VHDL.
The effort began in 1992 and was transferred to the IEEE 1076.4 sub-group in 1993. This group had already been in existence, working on a standard timing methodology. The working group published their first standard in 1996. It was updated in 2001 and withdrawn in 2009.

VITAL contained four main elements:
1) Model Development Specification document, which defines how ASIC libraries should be specified in VITAL-compliant VHDL in order to be simulated in VHDL simulators.
2) VHDL package Vital_Timing, defining standard types and procedures that support development of macro-cell timing models. The package contains routines for delay selections, timing violations checking and reporting and glitch detection.
3) VHDL package Vital_Primitives, defining commonly used combinatorial primitives provided both as functions and concurrent procedures and supporting either behavioral or structural modeling styles, e.g. VitalAND, VitalOR, VitalMux4, etc. The procedure versions of the primitives support separate pin-to-pin delay path and GlitchOnEvent glitch detection. Additionally, general purpose Truth Tables and State Tables are specified which are very useful in defining state machines and registers.
4) VITAL SDF map – specification that defines the mapping (translation) of Standard Delay Files (SDF), used for support timing parameters of real macro-cells, to VHDL generic values.

The 2000 edition also contained extensions to support memory modelling.