Published 8/23/2021 (by Mark LaPedus & Ed Sperling). . “Inside Intel’s Ambitious Roadmap” article link is here.
Ann Kelleher, senior vice president and general manager of Technology Development at Intel, sat down with Semiconductor Engineering to talk about the company’s new logic roadmap, as well as lithography, packaging, and process technology. What follows are excerpts of that discussion.
SE: Intel recently disclosed its new logic roadmap. Beyond Intel 3, the company is working on Intel 20A. With Intel 20A, you plan to introduce a RibbonFET in 2024. What is a RibbonFET and how does that propel Intel forward?
Kelleher: RibbonFET is our name for what other people in the industry call gate-all-around. Some people also call it a nanosheet or nanoribbon. It’s the next transistor architecture that takes us beyond finFET. We’re utilizing finFET until Intel 3 and will continue to improve finFET for that process. When we go to Intel 20A, we will be utilizing RibbonFET at approximately the same equivalent node as the rest of the industry.
SE: Intel was way ahead when it came to the finFET. The RibbonFET moves the industry forward again at the most advanced nodes. Can you pattern this technology using the current version of extreme ultraviolet (EUV) lithography?
Kelleher: We are using existing EUV tools at the 0.33 numerical aperture in our development of Intel 20A, which is planned for 2024. For our processes in 2025 and beyond, we are already partnering with ASML on high-NA EUV, which is the next numerical aperture for EUV. This next version of EUV tools allows us to get down to much smaller geometries. Beyond that point, we will use a mix of EUV, high-NA EUV, and other immersion and dry lithography layers as well.
SE: Why this sudden interest in high-NA EUV, and where do you plan to use it?
Kelleher: It allows us to move to much smaller geometries and much smaller pitches, and it also enables us to prolong the double-patterning EUV. Our interest in high-NA began a couple years ago. There’s really three companies that work with ASML, and all of us have worked over the years on EUV. Three years ago, we had a conversation with ASML about what’s next. There’s a recognition that the industry as a whole will need to go there. So we decided to put a stake in the ground, saying we will drive it for 2025. That’s going to be challenging. We’ve signed up to take the first equipment which means we will be the first ones on the learning curve. We didn’t have EUV on 10nm, which is now Intel 7, and we’re getting it on what we’re now calling Intel 4. We want to make sure that, as we go forward, we can maintain the leading edge of EUV’s capabilities. It will bring a significant amount of learning, but it also will enable us to continue the progression down to the smallest geometries.
SE: These are going to be pricey chips to develop. On a die, do you foresee that everything is going to be on a RibbonFET, or do you foresee this as a mix-and-match strategy with lots of different things? Intel seems to be going in two directions here. One is pushing down the lithography curve. The other side is that you have a number of different technologies, which are going into faster interconnects and advanced packaging.
Kelleher: From a product perspective, we have heterogeneous packaging. Basically, it’s a mix-and-match strategy using tiles, a bit like LEGO blocks. Product designers can pick and combine various technologies by which they want to build our products. Not everything needs to be on the latest nodes. Instead, you can pick the technology that is best suited for the aspect of the product that you want to deliver. Once we get to Intel 20A, our transistors will be built from RibbonFET from there on. But equally, we will continue to use and drive forward our advanced packaging technology. Then we can deliver and enable those different sets of building blocks to our products. For designers, they can mix and match to deliver leadership products to customers.
SE: Intel has expanded its advanced packaging portfolio, right?
Kelleher: Our advanced packaging technology starts with our 2.5D packaging, which is EMIB (Embedded Multi-die Interconnect Bridge). Then we have 3D packaging, which is Foveros. This involves a base die, on which you can stack chiplets. We also have Foveros Omni, which brings more benefits like cost savings, since the base die doesn’t have to be the same size as the top die. It also gives you power benefits. With Foveros Omni, we’re going to a smaller bump pitch, as well. Additionally, we introduced Foveros Direct, which is copper-to-copper bonding. This basically takes us almost to the monolithic level. When you do face-to-face bonding, you eliminate the solder, and you can get a significantly larger number of interconnects per square millimeter.
SE: Intel will push the finFET as far as possible to Intel 3, and then it will introduce its gate-all-around technology. In contrast, Samsung will introduce gate-all-around at 3nm. Why didn’t Intel do the same thing and bring up the RibbonFET at Intel 3?
Kelleher: We knew we had additional improvements we could make on our finFET roadmap, based in terms of what we get from an intrinsic optimization standpoint. So why not take those gains before making the transition to what is a very different architecture? The bottom line is, when is the right time to do it? Our transition to gate-all-around, or RibbonFET, is basically driven by our belief that we can deliver more from our existing finFET. Then we make our transition. Time will tell how the rest of the industry lands in terms of introducing gate-all-around.
SE: Several companies have been working on gate-all-around transistors for a long time. What are the challenges with the technology? Do the challenges involve EUV or other process steps?
Kelleher: Over recent years, EUV has matured significantly. It has reached more full-scale adoption within the process flow. This obviously makes it much easier in terms of the geometries you are going to print with it. In the earlier days of EUV, the question was whether EUV was going to be capable of doing all the layers that it is ultimately capable of. EUV capability, I will say, has truly progressed. It is a key enabler in terms of doing gate-all-around. Beyond those issues, you must also think about your stack height in terms of building the ribbons themselves and how high you want to go. You must also think about how you deal with the substrate and the isolation from the substrate. These are all challenges to be addressed, and we have a pathway to resolve all of them while getting the defects down and delivering in the time frame.
SE: One of the problems with increasing density is getting power to the various components on a chip. What’s the solution?
Kelleher: If we’re talking about power, I would like to talk about our PowerVia. Our PowerVia is a key innovation. When you look at the process flow today, the metallization is at the front of the wafer. Basically, it’s power delivery to the front of the wafer, to the transistors and the interconnect metallization. Our PowerVia innovation changes that. With the PowerVia, we’re able to deliver the power from the backside of the wafer. It allows for more room on the frontside of the wafer and gives us more ability to relax a little bit of our dimensions as we’re going down. At the same time, we’re able to get the power directly to the transistors without the power drop. It takes us to the next place in terms of dealing with the overall power delivery challenges.
SE: So as a result, can you actually lower the voltage? You have the conduit all set up in terms of driving the power through the chip, right?
Kelleher: The bottom line is, you have the power connected to where you need to at the back of the chip. In terms of power, the voltage optimization really comes down to what the designers want from the final product. On some processes, we want to run at a lower voltage. If you’re pushing the performance, you want to run it as a higher voltage. We tend to do both within our products. Overall, we will be able to provide and support what’s needed from the designers.
SE: Intel’s PowerVia looks similar to Imec’s Buried Power Rail (BPR). Is the PowerVia the same or different than BPR? And even with PowerVia, you still need the copper interconnects for the chips, right?
Kelleher: Buried Power Rail, at the highest level, is the same general theme. However it differs in how it’s achieved. We’re delivering the power from the back of the wafer to the transistor. Buried Power Rail is basically getting it from the front side, so you have a different architecture in achieving that. It is the key difference. We believe our way is actually the better way. You still need to have contacts to the transistors, which means dealing with contact resistance to address transistor signals that need to continue. We need to continue working on lowering the contact resistance of all of the various metals. The metallization schemes need to continue to reduce the overall resistance.
SE: Why did Intel change its node naming strategy?
Kelleher: The industry as a whole had become misaligned in node naming. If you do a search on Google, you will find explanations on why Intel’s 10nm is the equivalent of 7nm at the foundries. We had to think about making it easier to understand for our customers. Now when they look at our process nodes and the names, they are able to make better decisions. Why now? We introduced our IDM 2.0 vision in March and spent a lot of time over the last six months working on a very detailed roadmap. The roadmap lays out how we will get back to performance per watt parity and performance per watt leadership. Given that we were moving, we decided now is as good as time of any to rename them. We are now spending our time focusing on what we’re doing rather than explaining a node name.
SE: Today, Intel is shipping 10nm products based on its SuperFin technology. (SuperFin is a finFET technology.) Then, Intel’s next-generation 10nm products are based on an Enhanced SuperFin technology. Now, Intel has renamed this as Intel 7. What is Enhanced SuperFin?
Kelleher: We have 10nm SuperFin running in the factory today, and that is delivering our products like Tiger Lake. The Enhanced SuperFin, which is now Intel 7, is the next generation of SuperFin performance optimization.
SE: Recently, Intel experienced delays with its 7nm technology. (Intel’s original 7nm technology is now called Intel 4.) What’s the status of this technology?
Kelleher: We did a very public announcement on what was then called 7nm and is now Intel 4. At that point in time we reset our milestones in terms of overall process development and defect density. Since then we also began working on what was basically a parallel process to streamline the process flow and really increased our use of EUV within that process. With that we were able to switch over from the original version of the process flow to the new version going into this year. It’s going very well. We’ve reached our milestones over the last nine months, which gives me confidence that the work we’re doing is going to deliver. There are other changes we’ve made, too. I’ve spoken about how to put together our roadmap to get to leadership in performance per watt. First of all, we’ve identified a significant number of projects, and we are spending the R&D and capital to enable that. Second, we have world-class engineers within Intel’s Technology Development group. That was true before, and it is still true now. But how we’re working is changing. Where possible, and where it makes sense, we’re adopting industry standards. Design enablement is a key area for that. With the progression in EDA, we had to catch up so we could set our designers up for success.
SE: Intel is planning five nodes in four years to move to parity with your competitors and then a leadership position. This breaks all the rules from your past about a node every 18 to 24 months, right?
Kelleher: We will be releasing an Intel 7 product later this year. After that, we’re going to Intel 4. Intel 4 will be in production in the second half of 2022, with product releases in 2023. Intel 3 comes in during the second half of 2023. Intel 20A will follow in 2024 and then Intel 18A will come in after that. Our performance per watt gain from one node to the next is greater than any one on its own. This allows us to make up time against our benchmarks of external competition. But if you want to catch up and move ahead, you need to move faster. The methodologies we talked about will enable us to do that. I believe we have a very solid roadmap to deliver on this.
SE: How about Intel’s interactions with the rest of the industry?
Kelleher: We’ve also changed the way we’re working with our equipment vendors, our materials vendors, and our EDA suppliers. We don’t need to invent everything. There’s a lot of learning in the industry that is already proven by the equipment suppliers. Where possible, we’re pulling from the best in the ecosystem. This allows us to focus our resources on the innovations that will get us ahead. Also, we’ve done quite a lot in terms of risk assessment and identifying areas in the process where there could be higher risk. And then, out of that risk assessment, we can decide what types of contingency plans we need to build and determine how long we should develop those plans for – especially for areas that are higher risk. Obviously, you can’t create a contingency plan for everything, or else you’d be double developing everything. Across Intel 4 and nodes beyond that, we’ve been working on streamlining the process so we can have less complexity in hardware manufacturing.
SE: Intel has done a lot of work on chiplets and interconnects in advanced packages. As you move into more standardization and heterogeneous integration, do all of these components have to be characterized to Intel standards? Or do all of the components have to be Intel tiles?
Kelleher: If we go back and look at this over time, we’ve had tiles from within Intel and tiles from outside of Intel. It was relatively simple when you had two tiles. Today we’re up to 47 tiles in a package that brings silicon from different foundries and manufacturers together. At the product and design level, one of the things we have demonstrated is heterogeneous hardware from different hardware providers, as well as our FPGAs. This is a bit like in the past where we had many chips on a board. Now these chips are moving into the package, and we’re able to package them together. We provide the framework for the building blocks to come together so that the product designer can say, ‘For this product I need this unique set of attributes and here are our specs.’ This could involve many different factories, and the design teams collaborate very closely with the process teams and the packaging teams to integrate it all into one package. For all the products coming out in 2023, our packaging team has been working with the various places where all the silicon is coming from – internal and some external – and working on how everything will be compatible. Ultimately, the product is tested internally to ensure that all those standards work together. As an industry, standardization is an area where we can do more work together in the future.
SE: Where does hybrid bonding fit into Intel’s roadmap? Is it going to be bump pitch scaling for the foreseeable future?
Kelleher: There will be packages with hybrid bonding and there will be various techniques in the same package. We have 2.5D and 3D together in a package today because that enables flexibility for the given products. We will have hybrid bonding, too. It will be a mix-and-match. As for overall scaling of the bumps, we expect our first generation of HBI (hybrid-bonding interconnect) to be direct copper-to-copper, which will be a significant increase in terms of the density of bumps per mm². We believe we can get more than 10,000 per mm² with what we’re doing in our first generation of HBI.
SE: A lot of the guideposts like the ITRS roadmap have fallen by the wayside, while others like Moore’s Law seem to be less relevant. At the same time, the number of choices in a design are increasing. How does this impact what you build, particularly for foundry customers?
Kelleher: You’re trying to get to the best possible product for the customer at a given time. That’s the highest order part. But you have many more options on the menu, and it’s more of an à la carte menu than a fixed menu. In the past, everything was based on the node that you were working with. I go back to the design enablement team, as well as the design efforts between the process and packaging. These teams have a lot of active discussion and debate in terms of how we achieve the best possible answer for given products going forward. There are certain technical reasons for why one version of a tile will or won’t be used. There are many ways to get there, and the supply chain itself has become much more complicated. Depending on the particular product and its particular features, it becomes a discussion of how we get there with the most manufacturable version of tiles as well as the supply chain.
SE: Are any new materials being used here? We’ve seen adoption of cobalt and interest in ruthenium. How about others?
Kelleher: We have a very active set of ongoing programs between our components research and the materials suppliers, as well as our technology development with the suppliers. At this point, I’m not going to give you more new names and materials, but we’re not going to be fully done with Moore’s Law until every element on the periodic table is exhausted.
Multiple chips arranged in a planar or stacked configuration with an interposer for communication.
2.5D and 3D forms of integration
A memory architecture in which memory cells are designed vertically instead of using a traditional floating gate.
Transistors where source and drain are added as fins of the gate.
Next-generation wireless technology with higher data transfer rates, low latency, and able to support more devices.
We start with schematics and end with ESL
Important events in the history of logic simulation
Early development associated with logic synthesis
Commonly and not-so-commonly used acronyms.
Sensing and processing to make driving safer.
At newer nodes, more intelligence is required in fill because it can affect timing, signal integrity and require fill for all layers.
A collection of approaches for combining chips into packages, resulting in lower power and lower cost.
An approach to software development focusing on continual delivery and flexibility to changing requirements
How Agile applies to the development of hardware systems
A way of improving the insulation between various components in a semiconductor by creating empty space.
A collection of intelligent electronic environments.
The theoretical speedup when adding processors is always limited by the part of the task that cannot benefit from the improvement.
Semiconductors that measure real-world conditions
Analog integrated circuits are integrated circuits that make a representation of continuous signals in electrical form.
The design and verification of analog components.
A software tool used in software programming that abstracts all the programming steps into a user interface for the developer.
A custom, purpose-built integrated circuit made for a specific task or product.
An IC created and optimized for a market and sold to multiple companies.
Using machines to make decisions based upon stored knowledge and sensory input.
Code that looks for violations of a property
A method of measuring the surface structures down to the angstrom level.
A method of depositing materials and films in exact places on a surface.
ALE is a next-generation etch technology to selectively and precisely remove targeted materials at the atomic scale.
The generation of tests that can be used for functional or manufacturing verification
Issues dealing with the development of automotive electronics.
Time sensitive networking puts real time into automotive Ethernet.
Noise in reverse biased junctions
Verification methodology created by Mentor
IC manufacturing processes where interconnects are made.
Devices that chemically store energy.
Transformation of a design described in a high-level of abstraction to RTL
Security based on scans of fingerprints, palms, faces, eyes, DNA or movement.
A reverse force to electromigration.
Also known as Bluetooth 4.0, an extension of the short-range wireless protocol for low energy applications.
Transistor model
On-chip logic to test a design.
Interface model between testbench and device under test
C, C++ are sometimes used in design of integrated circuits because they offer higher abstraction.
Interconnect standard which provides cache coherency for accelerators and memory expansion peripheral devices connecting to processors.
Automotive bus developed by Bosch
CD-SEM, or critical-dimension scanning electron microscope, is a tool for measuring feature dimensions on a photomask.
Making CDC interfaces predictable
Fault model for faults within cells
Cell-aware test methodology for addressing defect mechanisms specific to FinFETs.
The CPU is an dedicated integrated circuit or IP core that processes logic and math.
A lab that wrks with R&D organizations and fabs involved in the early analytical work for next-generation devices, packages and materials.
Testbench component that verifies results
A process used to develop thin films and polymer coatings.
Design is the process of producing an implementation from a conceptual form
The design, verification, implementation and test of electronics systems into integrated circuits.
Exchange of thermal design information for 3D ICs
Asynchronous communications across boundaries
Dynamic power reduction by gating the clock
Design of clock trees for power reduction
The cloud is a collection of servers that run Internet software you can use on your device or computer.
Fabrication technology
Cobalt is a ferromagnetic metal key to lithium-ion batteries.
Metrics related to about of code executed in functional verification
Verify functionality between registers remains unchanged after a transformation
The plumbing on chip, among chips and between devices, that sends bits of data and manages that data.
Faster form for logic simulation
Complementary FET, a new type of vertical transistor.
Combinations of semiconductor materials.
Interconnect between CPU and accelerators.
The structure that connects a transistor with the first layer of copper interconnects.
A technique for computer vision based on machine learning.
Completion metrics for functional verification
Interference between signals
Crypto processors are specialized processors that execute cryptographic algorithms within hardware.
Companies supplying IP or IP services
A method of conserving power in ICs by powering down segments of a chip when they are not in use.
Data analytics uses AI and ML to find patterns in data to improve processes in EDA and semi manufacturing.
How semiconductors are sorted and tested before and after implementation of the chip in a system.
A data center is a physical building or room that houses multiple servers with CPUs for remote data storage and processing.
Data processing is when raw data has operands applied to it via a computer or server to process data into another useable form. This definition category includes how and where the data is processed.
A standard that comes about because of widespread acceptance or adoption.
The removal of bugs from a design
Deep learning is a subset of artificial intelligence where data representation is based on multiple layers of a matrix.
An observation that as features shrink, so does power consumption.
Actions taken during the physical design stage of IC development to ensure that the design can be accurately manufactured.
Techniques that reduce the difficulty and cost associated with testing an integrated circuit.
Protection for the ornamental design of an item
A physical design process to determine if chip satisfies rules defined by the semiconductor manufacturer
Locating design rules using pattern matching techniques.
Sources of noise in devices
Insertion of test logic for clock-gating
A wide-bandgap synthetic material.
Categorization of digital IP
Allowed an image to be saved digitally
A digital signal processor is a processor optimized to process signals.
A digital representation of a product or system.
A complementary lithography technology.
DNA analysis is based upon unique DNA sequencing.
Using deoxyribonucleic acid to make chips hacker-proof.
A patterning technique using multiple passes of a laser.
Colored and colorless flows for double patterning
Single transistor memory that requires refresh
Dynamically adjusting voltage and frequency for power reduction
Hardware Verification Language
A slower method for finding smaller defects.
Lithography using a single beam e-beam tool
The difference between the intended and the printed features of an IC layout.
Electromigration (EM) due to power densities
Electronic Design Automation (EDA) is the industry that commercializes the tools, methodologies and flows associated with the fabrication of electronic systems.
Levels of abstraction higher than RTL used for design and verification
Transfer of electrostatic charge.
An eFPGA is an IP core integrated into an ASIC or SoC that offers the flexibility of programmable logic without the cost of FPGAs.
Special purpose hardware used for logic verification
Capturing energy from the environment
Noise caused by the environment
A method for growing or depositing mono crystalline films on a substrate.
Programmable Read Only Memory that was bulk erasable.
Reuse methodology based on the e language
Methods for detecting and correcting errors.
Ethernet is a reliable, open standard for connecting devices by wire.
EUV lithography is a soft X-ray technology.
Finding out what went wrong in semiconductor design and manufacturing.
A way of including more features that normally would be on a printed circuit board inside a package.
Evaluation of a design under the presence of manufacturing defects
The lowest power form of small cells, used for home WiFi networks.
Ferroelectric FET is a new type of memory.
Reprogrammable logic device
The use of metal fill to improve planarity and to manage electrochemical deposition (ECD), etch, lithography, stress effects, and rapid thermal annealing.
A three-dimensional transistor.
non-volatile, erasable memory
Integrated circuits on a flexible substrate
An automotive communications protocol
Noise related to resistance fluctuation
A type of interconnect using solder balls or microbumps.
A transistor type with integrated nFET and pFET.
Formal verification involves a mathematical proof to show that a design adheres to a property
FD-SOI is a semiconductor substrate material with lower current leakage compared than bulk CMOS.
Coverage metric used to indicate progress in verifying functionality
Functional Design and Verification is currently associated with all design and verification functions performed before RTL synthesis.
Functional verification is used to determine if a design, or unit of a design, conforms to its specification.
A statistical method for determining if a test system is production ready by measuring variation during test for repeatability and reproducibility.
GaN is a III-V material with a wide bandgap.
A possible replacement transistor design for finFETs.
Power reduction techniques available at the gate level.
noise related to generation-recombination
A neural network framework that can generate new data.
Germany is known for its automotive industry and industrial machinery.
2D form of carbon in a hexagonal lattice.
An electronic circuit designed to handle graphics and video.
Adding extra circuits or software into a design to ensure that if one part doesn't work the entire system doesn't fail.
Fully designed hardware IP block
Use of special purpose hardware to accelerate verification
Historical solution that used real chips in the simulation process
Optimizing the design by using a single language to describe hardware and software.
Power creates heat and heat affects power
A dense, stacked version of memory with high-speed interfaces that can be used in advanced packaging.
Synthesis technology that transforms an untimed behavioral description into RTL
Defines a set of functionality and features for HSA hardware
HSAIL Virtual ISA and Programming Model, Compiler Writer, and Object Format (BRIG)
Runtime capabilities for the HSA architecture
Combines use of a public cloud service with a private cloud, such as a company's internal enterprise servers or data centers.
A data center facility owned by the company that offers cloud services through that data center.
What are the types of integrated circuits?
Hardware Description Language
Analog extensions to VHDL
A collection of VHDL 1076.1 packages
Modeling of macro-cells in VHDL
Boundry Scan Test
IEEE ratified version of Verilog
Standard for Verilog Register Transfer Level Synthesis
Extension to 1149.1 for complex device programming
Functional verification language
SystemC
Standard for integration of IP in System-on-Chip
IEEE Standard for Access and Control of Instrumentation Embedded within a Semiconductor Device
IEEE ratified version of SystemVerilog
Universal Verification Methodology
IEEE Standard for Design and Verification of Low-Power Integrated Circuits also known by its Accellera name of Unified Power Format (UPF)
Standard for Test Access Architecture for Three-Dimensional Stacked Integrated Circuits
Verification language based on formal specification of behavior
IEEE 802.1 is the standard and working group for higher layer LAN protocols.
IEEE 802.11 working group manages the standards for wireless local area networks (LANs).
IEEE 802.15 is the working group for Wireless Specialty Networks (WSN), which are used in IoT, wearables and autonomous vehicles.
"RR-TAG" is a technical advisory group supporting IEEE standards groups working on 802.11, 802.12, 802.16, 802.20, 802.21, and 802.22.
Standards for coexistence between wireless standards of unlicensed devices.
Enables broadband wireless access using cognitive radio technology and spectrum sharing in white spaces.
IEEE 802.3-Ethernet working group manages the IEEE 802.3-Ethernet standards.
Standard for Unified Hardware Abstraction and Layer for Energy Proportional Electronic Systems
Power Modeling Standard for Enabling System Level Analysis
Specific requirements and special consideration for the Internet of Things within an Industrial setting.
Wafer costs across nodes
Power optimization techniques for physical implementation
Performing functions directly in the fabric of memory.
Thermal noise within a channel
A set of basic operations a computer must support.
IGBTs are combinations of MOSFETs and bipolar transistors.
Integration of multiple devices onto a single piece of semiconductor
A semiconductor company that designs, manufactures, and sells integrated circuits (ICs).
A design or verification unit that is pre-packed and available for licensing.
Networks that can analyze operating conditions and reconfigure in real time.
Method to ascertain the validity of one or more claims of a patent
Buses, NoCs and other forms of connection between various elements in an integrated circuit.
Also known as the Internet of Everything, or IoE, the Internet of Things is a global application where devices can connect to a host of other devices, each either providing data from sensors, or containing actuators that can control some function. Data can be consolidated and processed on mass in the Cloud.
Fast, low-power inter-die conduits for 2.5D electrical signals.
Finding ideal shapes to use on a photomask.
Injection of critical dopants during the semiconductor manufacturing process.
Standard for integration of IP in System-on-Chip
The voltage drop when current flows through a resistor.
Terminology in ISO 26262
Standard related to the safety of electrical and electronic systems within a car
Standard to ensure proper operation of automotive situational awareness systems.
A standard (under development) for automotive cybersecurity.
The energy efficiency of computers doubles roughly every 18 months.
Languages are used to create models
Theories have been influential and are often referred to as "laws" and are discussed in trade publications, research literature, and conference presentations as "truisms" that eventually have limits.
Device and connectivity comparisons between the layout and the schematic
Cells used to match voltages across voltage islands
Measuring the distance to an object with pulsed lasers.
Low cost automotive bus
Deviation of a feature edge from ideal shape.
Removal of non-portable or suspicious code
LELE is a form of double patterning
A type of double patterning.
Light used to transfer a pattern from a photomask onto a substrate.
Coefficient related to the difficulty of the lithography process
Correctly sizing logic elements
Restructuring of logic for power reduction
A simulator is a software process used to execute a model of hardware
Methodologies used to reduce power consumption.
Verification of power circuitry
A technical standard for electrical characteristics of a low-power differential, serial communication protocol.
An approach in which machines are trained to favor basic behaviors and outcomes rather than explicitly programmed to do certain tasks. That results in optimization of both hardware and software to achieve a predictable range of results.
Uses magnetic properties to store data
Observation related to the amount of custom and standard content in electronics.
Tracking a wafer through the fab.
Noise sources in manufacturing
Semiconductor materials enable electronic circuits to be constructed.
A semiconductor device capable of retaining state information for a defined period of time.
Use of multiple memory banks for power reduction
Microelectromechanical Systems are a fusion of electrical and mechanical engineering and are typically used for sensors and for advanced microphones and even speakers.
A key tool for LED production.
Artificial materials containing arrays of metal nanostructures or mega-atoms.
Unstable state within a latch
Observation that relates network value being proportional to the square of users
Describes the process to create a product
Metrology is the science of measuring and characterizing tiny structures and materials.
A type of processor that traditionally was a scaled-down, all-in-one embedded processor, memory and I/O for use in very specific operations.
The integrated circuit that first put a central processing unit on one chip of silicon.
The integration of analog and digital.
Models are abstractions of devices
A midrange packaging option that offers lower density than fan-outs.
A way of stacking transistors inside a single chip instead of a package.
Observation related to the growth of semiconductors by Gordon Moore.
A mote is a micro-sensor.
An advanced form of e-beam lithography
An early approach to bundling multiple functions into a single package.
Increasing numbers of corners complicates analysis. Concurrent analysis holds promise.
Using a tester to test multiple dies at the same time.
Use of multi-threshold voltage devices
When a signal is received via different paths and dispersed over time.
A way to image IC designs at 20nm and below.
A durable and conductive material of two-dimensional inorganic compounds in thin atomic layers.
A hot embossing process type of lithography.
A type of field-effect transistor that uses wider and thicker wires than a lateral nanowire.
Optimizing power by computing below the minimum operating voltage.
Moving compute closer to memory to reduce access costs.
NBTI is a shift in threshold voltage with applied stress.
A method of collecting data from the physical world that mimics the human brain.
A compute architecture modeled on the human brain.
Nodes in semiconductor manufacturing indicate the features that node production line can create on an integrated circuit, such as interconnect pitch, transistor density, transistor type, and other new technology.
Random fluctuations in voltage or current on a signal.
Programmable Read Only Memory (PROM) and One-Time-Programmable (OTP) Memory can be written to once.
OSI model describes the main data handoffs in a network.
Verification methodology created from URM and AVM
Disabling datapath computation when not enabled
Method used to find defects on a wafer.
A way to improve wafer printability by modifying mask patterns.
The company that buys raw goods, including electronics and chips, to make a product.
Companies who perform IC packaging and testing - often referred to as OSAT
The ability of a lithography scanner to align and print various layers accurately on top of each other.
How semiconductors get assembled and packaged.
A high-speed signal encoding technique.
Outlier detection for a single measurement, a requirement for automotive electronics.
A patent is an intellectual property right granted to an inventor
A thin membrane that prevents a photomask from being contaminated.
Memory that stores information in the amorphous and crystalline phases.
A template of what will be printed on a wafer.
Light-sensitive material used to form a pattern on the substrate.
Design and implementation of a chip that takes physical placement, routing and artifacts of those into consideration.
PVD is a deposition method that involves high-temperature vacuum evaporation and sputtering.
Making sure a design layout works as intended.
A set of unique features that can be built into a chip but not cloned.
A small cell that is slightly higher in power than a femtocell.
Lowering capacitive loads on logic
An algorithm used ATPG
Hardware Verification Language, PSS is defined by Accellera and is used to model verification intent in semiconductor design.
Components of power consumption
Power domain shutdown and startup
Definitions of terms related to power
Moving power around a device.
How is power consumption estimated
Reducing power by turning off parts of a design
Special flop or latch used to retain the state of the cell when its main power supply is shut off.
Addition of isolation cells around power islands
Power reduction at the architectural level
Ensuring power control circuitry is fully verified
An integrated circuit that manages the power in an electronic device or module, including any device that has a battery that gets recharged.
A power semiconductor used to control and convert electric power.
A power IC is used as a switch or rectifier in high voltage power applications.
Noise transmitted through the power delivery network
Controlling power for power shutoff
Techniques that analyze and optimize power in a design
Test considerations for low-power circuitry
Fundamental tradeoffs made in semiconductor design for power, performance and area.
The design, verification, assembly and test of printed circuit boards
Data centers and IT infrastructure for data storage and computing that a company owns or subscribes to for use only by that company.
power optimization techniques at the process level
Variability in the semiconductor manufacturing process
A measurement of the amount of time processor core(s) are actively in use.
An integrated circuit or part of an IC that does logic and math processing.
Verification language based on formal specification of behavior
Data storage and computing done in a data center, through a service offered by a cloud service provider, and accessed on the public Internet.
A different way of processing data using qubits.
RF SOI is the RF version of silicon-on-insulator (SOI) technology.
Random trapping of charge carriers
The process of rapidly heating wafers.
Critical metals used in electronics.
Read Only Memory (ROM) can be read from but cannot be written to.
An artificial neural network that finds patterns in data using other data stored in memory.
Copper metal interconnects that electrically connect one part of a package to another.
Design verification that helps ensure the robustness of a design and reduce susceptibility to premature or catastrophic electrical failures.
Materials used to manufacture ReRAMs
Memory utilizing resistive hysteresis
Synonymous with photomask.
A proposed test data standard aimed at reducing the burden for test engineers and test operations.
An open-source ISA used in designing integrated circuits at lower cost.
Trusted environment for secure functions.
An abstraction for defining the digital portions of a design
Optimization of power consumption at the Register Transfer Level
A series of requirements that must be met before moving past the RTL phase
Verification methodology based on Vera
Algorithm used to solve problems
Additional logic that connects registers into a shift register or scan chain for increased test efficiency.
Mechanism for storing stimulus in testbench
Testbench support for SystemC
A form of double patterning.
Subjects related to the manufacture of semiconductors
Methods and technologies for keeping data safe.
Combining input from multiple sensor types.
Sensors are a bridge between the analog world we live in and the underlying communications infrastructure.
A transmission system that sends signals over a high-speed connection from a transceiver on one chip to a receiver on another. The transceiver converts parallel data into serial stream of data that is re-translated into parallel on the receiving end.
In semiconductor development flow, tasks once performed sequentially must now be done concurrently.
Sweeping a test condition parameter through a range and obtaining a plot of the results.
When channel lengths are the same order of magnitude as depletion-layer widths of the source and drain, they cause a number of issues that affect design.
Quantization noise
A class of attacks on a device and its contents by analyzing information using different access methods.
A wide-bandgap technology used for FETs and MOSFETs for power transistors.
The integration of photonic devices into silicon
A simulator exercises of model of hardware
Special purpose hardware used to accelerate the simulation process.
Disturbance in ground voltage
Single transistor DRAM
Wireless cells that fill in the voids in wireless infrastructure.
Synthesizable IP block
Verification methodology utilizing embedded processors
Defines an architecture description useful for software design
Circuit Simulator first developed in the 70s
A type of neural network that attempts to more closely model the brain.
A type of MRAM with separate paths for write and read.
A secure method of transmitting data wirelessly.
A patent that has been deemed necessary to implement a standard.
The most commonly used data format for semiconductor test information.
Standards are important in any industry.
SRAM is a volatile memory that does not require refresh
Constraints on the input to guide random generation process
Random variables that cause defects on chips during EUV lithography.
An advanced type of MRAM
Use of Substrate Biasing
Coupling through the substrate.
Network switches route data packet traffic inside the network.
Type of DRAM with faster transfer
A method for bundling multiple ICs to work together as a single chip.
A system on chip (SoC) is the integration of functions necessary to implement an electronic system onto a single substrate and contains at least one processor
A class library built on top of the C++ language used for modeling hardware
Analog and mixed-signal extensions to SystemC
Industry standard design and verification language
Google-designed ASIC processing unit for machine learning that works with TensorFlow ecosystem.
Software used to functionally verify a design
Noise related to heat
Through-Silicon Vias are a technology to connect various die in a stacked die configuration.
Basic building block for both analog and digital integrated circuits.
Minimizing switching times
A multi-patterning technique that will be required at 10nm and below.
A type of transistor under development that could replace finFETs in future process technologies.
Standard for safety analysis and evaluation of autonomous vehicles.
The Unified Coverage Interoperability Standard (UCIS) provides an application programming interface (API) that enables the sharing of coverage data across software simulators, hardware accelerators, symbolic simulations, formal tools or custom verification tools.
Accellera Unified Power Format (UPF)
Verification methodology
SystemVerilog version of eRM
User interfaces is the conduit a human uses to communicate with an electronics device.
Patent to protect an invention
Hardware Verification Language
A pre-packaged set of code used for verification.
A standardized way to verify integrated circuit designs.
A document that defines what functional verification is going to be performed
Hardware Description Language in use since 1984
Procedural access to Verilog objects
Analog extensions to Verilog
Hardware Description Language
An abstract model of a hardware system enabling early software execution.
Verification methodology built by Synopsys
Using voice/speech for device command and control.
Memory that loses storage abilities when power is removed.
Use of multiple voltages for power reduction
The basic architecture for most computing today, based on the principle that data needs to move back and forth between a processor and memory.
Verifying and testing the dies on the wafer after the manufacturing.
The science of finding defects on a silicon wafer.
3D memory interface standard
Wired communication, which passes data through wires between devices, is still considered the most stable form of communication.
A way of moving data without wires.
IC interconnect architecture
X Propagation causes problems
A data-driven system for monitoring and improving IC yield and reliability.
A vulnerability in a product’s hardware or software discovered by researchers or attackers that the producing company does not know about and therefore does not have a fix for yet.