tag: Intel

Power Delivery Challenges For AI Chips
By Gregory Haley - 19 Jun, 2025 - Comments: 0

As artificial intelligence (AI) workloads grow larger and more complex, the various processing elements being developed to process all that data are demanding unprecedented levels of power. But delivering this power efficiently and reliably, without degrading signal integrity or introducing thermal bottlenecks, has created some of the toughest design and manufacturing challenges in semiconducto... » read more

Are Larger Reticle Sizes On The Horizon?
By Katherine Derbyshire - 19 Jun, 2025 - Comments: 0

Making high-NA EUV lithography work will take a manufacturing-worthy approach to stitching together circuits or a wholesale change to larger masks. Circuit stitching between the exposure fields is challenging the design, yield and manufacturability of the high-NA (0.55) EUV transition. The alternative is a radical change from 6x6-inch to 6x11-inch masks that would eliminate stitching, but it... » read more

TSMC: King Of Data Center AI
By Geoff Tate - 16 Jun, 2025 - Comments: 0

Large language models (LLMs like ChatGPT) are driving the rapid expansion of data center AI capacity and performance. More capable LLM models drive demand and need more compute. AI data centers require GPUs/AI Accelerators, switches, CPUs, storage and DRAM. About half of semiconductors are consumed by AI data centers now. This percentage will be much higher by 2030. TSMC has essentially 1... » read more

Tackling Advanced Chip Manufacturing Challenges
By Christophe Begue - 10 Jun, 2025 - Comments: 0

Intel and PDF Solutions are deepening their partnership to address the growing complexity of semiconductor manufacturing at advanced nodes, according to a recent discussion between Intel CEO Lip-Bu Tan and PDF Solutions CEO John Kibarian at the Direct Connect Intel Foundry event in April. During the presentation, Kibarian highlighted how the two companies have been collaborating for approxim... » read more

Co-Packaged Optics Reaches Power Efficiency Tipping Point
By Laura Peters - 02 Jun, 2025 - Comments: 0

Commercialization has started for network switches based on co-packaged optics (CPO), which are capable of routing signals at terabits per second speeds, but manufacturing challenges remain regarding fiber-to-photonic IC alignment, thermal mitigation, and optical testing strategies. By moving the optical-to-electronic data conversion as close as possible to the GPU/ASIC switch in data center... » read more

Chip Industry Week in Review
By The SE Staff - 23 May, 2025 - Comments: 0

Podcast: imec's roadmap and a one-on-one interview with the European research house's chief strategy officer. China's Xiaomi debuted an in-house-designed 10-core mobile SoC built on a 3nm process. The company did not identify the foundry. It also announced plans to invest 50 billion yuan (~$7B) over the next decade to develop high-end smartphone chips, as part of a 200 billion yuan (~$28B) c... » read more

Advanced Packaging Depends On Materials And Co-Design
By Katherine Derbyshire - 22 May, 2025 - Comments: 0

Multi-die assemblies offer significant opportunities to boost performance and reduce power, but these complex packages also introduce a number of new challenges, including die-to-RDL misalignment, evolving warpage profiles, and CTE mismatch. Heterogeneous integration — an umbrella term that covers many different applications and packaging requirements — holds the potential to combine com... » read more

Chip Industry Technical Paper Roundup: May 20
By Linda Christensen - 20 May, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=432 /] Find more semiconductor research papers here. » read more

Floorplanning Method For Reducing Thermally-Induced Structural Stress In Chiplet Packages (Penn State, Intel, ASU et al.)
By Technical Paper Link - 14 May, 2025 - Comments: 0

A new technical paper titled "STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration" was published by researchers at Pennsylvania State University, Intel, Arizona State University and University of Notre Dame. Abstract "Chiplet-based architectures and advanced packaging has emerged as transformative approaches in semiconductor design. While conventional ph... » read more

Chip Industry Week in Review
By The SE Staff - 09 May, 2025 - Comments: 0

Check out the Inside Chips podcast for our behind-the-scenes analysis. The U.S. government is rescinding a Biden-era AI export rule that would have imposed complex restrictions on how U.S. chip and AI technology is sold abroad, a move welcomed by companies like Nvidia, reports Bloomberg. While new, simpler guidelines are expected in the coming months, the decision introduces short-term uncer... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy