Reducing stress in chiplets; CFETs beyond 3nm; RISC-V eGPUs for TinyAI; LLM for VHDL MPU design; cache side-channel attacks on LLMs; memory prefetching for HPC processors; EUV scatterometry on 2D interconnect; zinc sulfide on BEOL compatible substrates.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| STAMP-2.5D: Structural and Thermal Aware Methodology for Placement in 2.5D Integration | Penn State Univ. Intel, Arizona State Univ. and Univ. of Notre Dame |
| CFET Beyond 3 nm: SRAM Reliability under Design-Time and Run-Time Variability | TU Munich and IIT Kanpur |
| e-GPU: An Open-Source and Configurable RISC-V Graphic Processing Unit for TinyAI Applications | EPFL |
| Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors | IBM |
| Spill The Beans: Exploiting CPU Cache Side-Channels to Leak Tokens from Large Language Models | MITRE and Worcester Polytechnic Institute |
| Memory Prefetching Evaluation of Scientific Applications on A Modern HPC Arm-based Processor | Jülich Supercomputing Centre and KTH Royal Institute of Technology |
| Coherent EUV scatterometry of 2D periodic structure profiles with mathematically optimal experimental design | University of Colorado, NIST, Samsung and KMLAb |
| Textured growth and electrical characterization of Zinc Sulfide on back-end-of-the-line (BEOL) compatible substrates | USC, Lawrence Berkeley National Laboratory and TSMC |
Find more semiconductor research papers here.
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