Chip Industry Technical Paper Roundup: Mar. 3


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance 🔗 KAIST, Panmnesia, Peking University, Hanyang University, Pennsylvania State University Sputtering-driven formation of interstitial oxygen for intrinsic NIR detec... » read more

Chip Industry Week In Review


Big Deals and Fundings Rapidus secured US$1.7B in a new funding round from the Japanese government and the private sector to ramp 2nm production by next year. Open AI announced a $110B in new funding, with $30B from Nvidia, $30B from Softbank and $50B from Amazon. In a $100B multi-year deal, Meta will power its AI infrastructure with up to 6GW of AMD's GPUs. SambaNova and Intel ar... » read more

An FPGA-based Accelerator Addressing Bottlenecks in GNN Preprocessing (KAIST et al.)


A new technical paper "AutoGNN: End-to-End Hardware-Driven Graph Preprocessing for Enhanced GNN Performance" was published by researchers at KAIST, Panmnesia, Peking University, Hanyang University, and Pennsylvania State University. Abstract "Graph neural network (GNN) inference faces significant bottlenecks in preprocessing, which often dominate overall inference latency. We introduce Au... » read more

Research Bits: Dec. 2


Ionothermoelectric cooling Researchers from the University of Osaka, University of Tokyo, and Japan's National Institute of Advanced Industrial Science and Technology proposed an ionothermoelectric cooling strategy for chips that enhances cooling by driving the flow of ions through nanoscale channels. “We fabricated a nanosized pore in a semiconductor membrane and surrounded the nanopore ... » read more

Chip Industry Week in Review


Retaliations and countermoves leading up to planned trade talks between the U.S. and China led experts to wonder, 'Who's winning?' New activity on this front: China issued questionnaires to some U.S. semiconductor firms as part of an anti-dumping probe, demanding detailed data on sales, profit margins, logistics costs and Chinese customer names for analog chips. The probe appears aimed at ... » read more

Research Bits: August 11


Fluorine-free ferroelectrics Researchers from Case Western Reserve University, Vanderbilt University, Pennsylvania State University, Brookhaven National Laboratory, Tennessee State University, and University of Tennessee created a ferroelectric polymer for infrared detectors and sensors in wearable electronics that is made without fluorine. The most common ferroelectric polymer is poly(vinylid... » read more

Research Bits: July 1


Copper-to-copper bonding for GaN integration Researchers from MIT, Georgia Tech, and Air Force Research Laboratory propose a bonding process to integrate gallium nitride (GaN) transistors onto standard silicon CMOS chips. They used the process to create a power amplifier. “We wanted to combine the functionality of GaN with the power of digital chips made of silicon, but without having to ... » read more

Research Bits: June 9


InGaOx GAA transistor Researchers from the University of Tokyo created a gate-all-around transistor made from gallium-doped indium oxide (InGaOx). Doping indium oxide with gallium suppressed oxygen vacancies, improving transistor reliability. "We wanted our crystalline oxide transistor to feature a 'gate-all-around' structure, whereby the gate, which turns the current on or off, surrounds t... » read more

Chip Industry Technical Paper Roundup: June 3


New technical papers recently added to Semiconductor Engineering’s library: [table id=436 /] Find more semiconductor research papers here. » read more

SRAM Cell Scaling With Monolithic 3D Integration Of 2D FETs (Penn State)


A new technical paper titled "Enabling static random-access memory cell scaling with monolithic 3D integration of 2D field-effect transistors" was published by researchers at The Pennsylvania State University. Abstract "Static Random-Access Memory (SRAM) cells are fundamental in computer architecture, serving crucial roles in cache memory, buffers, and registers due to their high-speed perf... » read more

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