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Hardware Description Language in use since 1984


Verilog was invented by Phil Moorby and released by Gateway Design Automation in 1984 along with a logic simulator, Verilog-XL. Gateway was purchased by Cadence in 1990 but it remained a closed proprietary language, although it was licensed to Synopsys for their emerging logic synthesis program, thus creating the first RTL flow.

The name Verilog comes from the merger of the words VERIfy and LOGic.

When VHDL was given to the IEEE for standardization in 1986, Cadence opened the language up and created Open Verilog International (OVI) to manage the language. It was later handed to the IEEE and became IEEE 1364-1995. Significant extensions were made to the language in 2001 and additional minor changes in 2005.

In 1991, Chronologic Simulation created the first compiled code simulator version of Verilog – VCS.

In 1995, Verilog-A added a set of extension for the support of analog modeling which primarily came from the Spectre language, a variant of the SPICE circuit simulator, and owned by Cadence.

In 2005 a major set of extensions were made to Verilog which added hardware verification languages (HVLs) to the existing hardware design language (HDL). Many of these extensions came from SuperLog and Vera – languages held at that time by Synopsys. The new language was called SystemVerilog and was also handed over to the IEEE to become IEEE 1800-2005.

A combined mixed-signal language (Verilog-AMS) was developed and released in 2005. The Verilog-AMS standard supports analog and mixed-signal designs at three levels: transistor/gate, transistor/gate-RTL/behavioral, and mixed transistor/gate-RTL/behavioral circuit levels. An Accellera committee is currently working to align Verilog-AMS with the SystemVerilog work of the IEEE 1800, for inclusion of AMS capabilities in a new “SystemVerilog-AMS” standard.

An update was made to SystemVerilog in 2009 and at that point the original Verilog standard was retired.

Advanced Chip Design, Practical Examples in Verilog

Verilog by Example: A Concise Introduction for FPGA Design

Digital Design and Verilog HDL Fundamentals

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