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FishTail Design Automation, Inc.

Automatic generation and verification of timing constraints


FishTail Design Automation’s solutions enable generation of clock constraints and timing exceptions, formal constraint verification and interactive debug, and checking, mapping, promotion, demotion, and equivalence verification. The company’s SDC generation solution reads the RTL for a design and generates clock definitions, I/O delays, clock groups, clock senses, and timing exceptions for the design.

Its SDC verification flow reads the RTL description for a design, along with either gate or RTL-level Tcl constraints. Constraints are mapped to the design, with syntax and constraint application issues flagged, and formally proven. The SDC verification technology eliminates the need for gate-level simulation.


FishTail Design Automation was acquired by Synopsys in September 2022.