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Power Delivery Network (PDN)

Moving power around a device.
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Description

Getting power around a semiconductor device is complicated and expensive. It generally starts at a power supply and transferred by wires to a printed circuit board. Attached to that board are one or more ICs. Traces on the PCB connect from the pads where the power supply wires are connected to the pad where power will be transferred to the chip. Those PCB traces may also involve vias that go through the PCB. To go from the chip pad into the chip will involve some kind pin or bump and that has to be connected to the semiconductor surface – often involving a wire or other metal conductor and solder. Then a series of metal layer traces and vias, and potentially traces within the silicon, connect the transistors to the supply. Along that path, a set of resistances, capacitance and inductances are inherited that mean that what appears at the transistor is not a perfect replication of what came out of the power supply.

Voltage regulators or converters may also be inserted anywhere along that path to provide the necessary voltages for various pieces of the circuit. In low power designs, switches may exist within the power supply to enable power to be removed from some parts of the circuit to reduce the leakage power. Because of peak current demands, capacitors may be added the retain enough charge to meet the instantaneous demand and are then recharged when less current is required.

Historically, the power delivery network (PDN) was overdesigned by adding significant margins to all aspects of the network, thus ensuring that timing or functional failures were not caused by an inadequate design. More recently, that level of margin can no longer be tolerated and so much more attention is being paid to the PDN and much more analysis is being performed on it. This is sometimes called power integrity analysis.

There are several aspects to this analysis. IR drop looks at the potential for the voltage on a transistor not being adequate and impacting timing and potential functional integrity. Electromigration looks at the likelihood that traces will age over time resulting in devices that prematurely fail. Noise analysis looks to see if sensitive circuitry will be affected either directly or through coupling.