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IEEE 1364.1-Verilog RTL Synthesis

Standard for Verilog Register Transfer Level Synthesis


IEEE 1364.1-2002 Standard for Verilog Register Transfer Level Synthesis

This standard describes a standard syntax and semantics for Verilog HDL based RTL synthesis. It defines the subset of IEEE 1364 (Verilog HDL) that is suitable for RTL synthesis and defines the semantics of that subset for the synthesis domain.

The purpose of this standard is to define a syntax and semantics that can be used in common by all compliant RTL synthesis tools to achieve uniformity of results in a similar manner to which simulation and analysis tools use the IEEE 1364 standard. This will allow users of synthesis tools to produce well defined designs whose functional characteristics are independent of a particular synthesis implementation by making their designs compliant with this standard.

According to the IEEE, this standard has been withdrawn.