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Verification methodology built by Synopsys


The Verification Methodology Manual (VMM) was a set of practices for creation of reusable verification environments in SystemVerilog. Created by Synopsys, VMM harnesses language features such as object-oriented programming, randomization, constraints, functional coverage.

The VMM methodology, defined in the book Verification Methodology Manual for SystemVerilog, provides industry best practices developed since 2005. It includes a set of guidelines, recommendations, and rules help engineers prevent common mistakes while creating interoperable verification components. The VMM standard library provides the foundation base classes for building advanced testbenches, while the VMM applications provide higher-level functions for improved productivity.

Synopsys donated the source code of the VMM methodology to Accellera in 2008.

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