Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here.

Cookbook Overview Diagram

The Universal Verification Methodology (UVM) is a standard library of SystemVerilog classes that supports a modular, reusable testbench architecture for constrained-random functional verification. Meanwhile, Mentor’s UVM Cookbook is the premier how-to guide to the UVM. The 547-page Cookbook shows you how to take full advantage of the UVM in a wide range of functional verification projects. More than an introduction of UVM processes, the Cookbook provides a powerful, online, searchable guide for deploying the UVM. It quickly gets you over the “blank page” hump by providing downloadable examples that can serve as templates for creating your own environments.

The UVM Cookbook is full of authoritative explanations, not only of advanced verification concepts but of specific examples that you can modify for your particular circumstances. If you are at the beginning of your verification career or just new to SystemVerilog or the UVM, the UVM Cookbook will help you jump start your projects. Seasoned pros will also find these explanations, examples, and templates to be highly useful productivity tools. If you get stuck on anything UVM, the UVM Cookbook is structured so that you can quickly find out what to do.

The UVM Cookbook represents a long collaborative effort between Mentor and our users. The first editions were published in hardcopy form, beginning with the Advanced Verification Methodology (AVM) in 2006 and progressing through what became the Open Verification Methodology (OVM) and ultimately the UVM.

When the UVM came out, we decided to put it online to allow us to stay current as things were being refined and added to the Accellera standard. This latest update was prompted by the adoption of UVM as IEEE 1800.2 in November 2017, with the subsequent release by Accellera of a compatible Reference Implementation library.

A significant change in the industry since UVM was first introduced is the incredible increase in the size and complexity of designs. What used to be considered a “system” back then is now considered just one piece of a much larger system today. This has greatly increased the demand for faster execution platforms on which to perform verification, and as such we are seeing more and more users adopting emulation, hardware acceleration, and FPGA prototyping as part of their functional verification flows. The requirement to preserve existing UVM infrastructures throughout a project has led us to update our recommendation for how to organize a UVM testbench, particularly at the level at which the UVM testbench interacts with the device under test (DUT).

Thus, a prominent addition to the UVM Cookbook is the introduction of a new emulation-friendly testbench architecture based on the use of “split transactors,” where, instead of a driver/monitor component having a reference to a pin-level SystemVerilog interface, the transactor will have a reference to a “BFM interface” that supports a set of transaction-level methods called from the transactor. This BFM interface will then drive pin-level signals that are connected to the DUT. This organization allows for the higher-bandwidth transaction-level communication to occur across the simulation/emulation boundary, with the BFM interface and all other HDL content executing in the emulator and all class-based UVM components executing in the simulator, as is done in the UVM Framework and by all our Questa VIP (QVIP) components.

At the same time, we wanted to update much of the material from the previous edition of the UVM Cookbook, so we completely revamped and updated all the examples. They are all self-running and self-checking, and they are all IEEE 1800.2-compliant as well.

Those familiar with older editions of the UVM Cookbook may notice other improvements, including the following changes:

• All-new “UVM Basics” and “UVM Messaging” chapters
• Streamlined “Testbench Architecture” and “DUT-Testbench Connections” chapters
• Updated “Register Abstraction Layer” chapter to follow 1800.2
• Updated “Testbench Acceleration” and “UVM Connect” chapters
• Revised Appendices
• And no more OVM references, which have been moved to an online archive

We trust these revisions will be of value to both new and old members of the UVM community. One of the greatest advantages of publishing this book online is that readers can provide immediate, detailed feedback and we can respond quickly to that feedback without having to wait for another hardcopy edition.

I am continually approached by people at trade shows and seminars who thank us for the material in the UVM Cookbook and elsewhere on the Verification Academy and tell me how useful they have found it. I am excited to welcome even more people into the UVM Cookbook community. We hope this fully updated edition of the cookbook will help you incorporate the UVM into your particular application and improve your functional verification process.

The UVM Cookbook is available online here.